Interposer technologies are gathering more importance in IC packaging as the industry continues miniaturization trends in microfabrication nodes and IC packaging to meet design and utility needs in consumer electronics. Furthermore,IC packaging is widely seen as a method to prolong Moore’s law. Historically,silicon has been the material of interest for interposer materials given its prevalence in IC production,but it presents many technical and costs hurdles. In contrast,glass interposer technology presents a low cost alternative,yet attempts at producing advanced through glass vias (TGVs) arrays using traditional methods,such as laser ablation,have inherent process flaws,such as reduced interposer mechanical strength and debris sputtering among others.
In this extended abstract we present 3D Glass Solutions’ efforts in using our proprietary APEX™ Glass ceramic to create various interposer technologies. This extended abstract will present on the production of large arrays of 10 micron diameter TGVs,with 20 micron center-to-center pitch,in 100 micron thick APEX™ Glass ceramic and the comparisons of wet etching of APEX™ Glass vs. laser ablation.

The Printed Circuit Board (PCB) is the backbone of electronics and a large number of consumer devices. The challenge to put more function in a smaller space requires more components utilizing smaller bond pads,smaller lines and tighter pitch. The electronic packaging industry has aggressively pursued novel ways to shrink and stack multilayer boards inside smaller volumes. Industry is approaching serious obstacles in the continued size reduction requirements with the need for wires,epoxy,vias,solder and sometimes bolts and screws to mount the boards. The next logical step is to move beyond 2D stacking,which is 2.5D to make 3D packages and to utilize the 3rddimension directly. Eliminate the traditional 2D FR4 board and the wires,epoxies,vias and solder and make the next generation packages utilizing the 3rddimension; the Printed Circuit Structure (PCS). The PCS concept will allow passives,actives and even antennas to move out of the XY plane and into the XZ and YZ planes. This new dimension will appear to be very complex and next generation circuit optimization will be required,but the end result will net a significant improvement in volume utilization. In addition,if new materials are developed and utilized properly,the PCS will be the box or the package thus eliminating all the bolts and screws necessary to mount a PCB in a traditional box or package,thus again saving space and reducing weight. nScrypt and the University of Texas at El Paso will present 3D Printing of Printed Circuit Structures. A demonstration of true 3D electronic structures will be demonstrated and shown as well novel approaches which utilize Computer Aided Design (CAD) to 3D Printing which will include the electronics portion.

Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections,on the other hand,has proved to be more efficient and,even though two interposers are required,more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology. Research results will be presented that will illustrate multiple methods for forming smaller and finer pitch contacts on the base package section using existing wire-bond and transfer mold technology. The process developed utilizes copper bond-wire that enables several profile variations and can furnish an array configured contact pitch at or below 200µm. The benefits are immediately seen. This interconnect solution is very economical and lends itself to a wide variety of 3D
packaging,including multiple-rows and area array,fan-in and fan-out,flat or step mold,bond wires present on bottom or top package,bottom package face-up or face-down die orientations.

MultiChip Module Status
•It isn’t a new idea since back in the 1980’s everyone was trying to combine different components into a single package
•It started with Hybrids then different forms of SMT
•Since that time many methods have been used to bring higher operating performance to electronic assemblies
•Coined phrases such as System-in-a Package,Package-on-Package,or Application Specific I/C abounded
•However with the breakthrough of being able to create a Via between wafers (Through- Silicon-Vias) other new forms are evolving

The banning of Pb in electronic component termination finishes has flushed through the supply chain making it impossible in some cases for hi-reliability users to purchase Pb containing interconnects. It has also led to increasing problems with tin whiskers. Many end-users are now reterminating components with SnPb solder. This paper will discuss the results of a recent joint industry project undertaken at NPL to evaluate the retermination process on a range of electronic package styles. Details will be given of package styles covered,evaluation techniques employed,inter-comparison of reliability data,results and areas of concern.

As reliability requirements increase,especially for defense and aerospace applications,the need to characterize components used in electronic assembly also increases. OEM and EMS companies look to perform characterizations as early as possible in the process to be able to limit quality related issues and improve both assembly yields and ultimate device reliability. In terms of BGA devices,higher stress conditions,RoHS compatible materials and increased package densities tend to cause premature failures in intermetallic layers. Therefore it is necessary to have a quantitative and qualitative test methodology to address these interfaces.
Typically,solder ball shear or pull testing is employed to measure the interfacial strength,sometimes requiring very high speeds to do so. While there is no current industry accepted specification on proper test speeds,strength or energy metrics,procedures do exist which allow for relevant comparisons. These tests are always run on unassembled BGA devices,so the interaction with the PCB is completely removed. While the data is useful for the component manufacturer,the risk is that the test does not fully represent the final assembly in terms of metallurgical condition. Specifically when BGA components using a Nickel-Gold surface finish are soldered to PCBs with a Cu-based pad (ie,Cu-OSP,ImmAg,ImmSn or HASL),there will be additional Cu dissolved into the solder joint. The addition of this copper can have an important effect on the intermetallic structure at the ENIG pad. Current mechanical solder ball testing procedures on unassembled BGA devices do not accurately duplicate the condition of this intermetallic structure. The test results on ENIG pads will then not necessarily correlate to actual manufacturing reliability.
From this research we have determined that generating an intermetallic morphology that is similar to a standard mass reflow surface mount process is not straight forward. The method used to add Cu to the ENIG pad and lead-free solder system will affect the morphologies at the electroless Ni substrate and therefore the mechanical properties of the intermetallic. Data is presented on the intermetallic strengths and failure modes of two bond pull test methods. Specifically Hot Bump Pull (HBP) and Cold Bump Pull (CBP) testing are compared where Cu is added by the copper pins of the HBP tester or by Cu power in a second reflow followed by CBP testing.

With the adoption of RoHS and implementation of Lead Free solders a major concern is how this will impact reliability. Both commercial and military hardware are impacted by this change even though military hardware is considered exempt from the requirements of RoHS. As the supply chain has moved to the new lead free alloys both markets are being forced to understand these impacts and form risk mitigation strategies to deal with the change. This paper documents the effect of mixing Leaded and Lead Free alloys on BGA devices and how this impacts reliability. Three of the most common pitch BGA packages are included in the study to determine if the risk is the same as pitches decrease. Metallurgical analysis was performed utilizing cross-sections and SEM to study the alloying of tin/lead and tin/silver/copper both separately and combined. MIL-STD-883 Method 1010.8 Temperature Cycling was used to accelerate fatigue life of the samples and testing of those samples was performed at regular intervals using a bed of nails tester. Various reflow soldering temperatures were used to assemble the different combinations of alloys. Under-filling of assembled BGA’s was also studied as a risk mitigation strategy.

Printed & Flexible Electronics
• Development Waves – 1st,2nd,and 3rd
• Essentials
• Products and Applications
• Technology and Infrastructure Development
• Printed & Flexible Electronics Pipeline – Experts Only*

ITO nanoparticles were successfully printed on glass with the AccuPress Gravure System
•A wide range of sheet resistivity values was achieved with different engraving resolutions of the gravure cells.
•A sheet resistivity as low as 415 O/? was achieved through the use of high temperature sintering and 1000 O/? was achieved through the photonic sintering.
•Visible Light transmission above 88% was obtained,regardless of the sintering method of ITO films.

HoP Mitigation is addressed with respect to solder paste,components,inspection,process and the environment.
Graping minimization recommendations are given with data driven suggestions.