The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects,the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly,there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.
The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.
The DOE will include an 8 run experiment with 2 center point runs for a total of 10 runs. This experimental setup is a half fractional factorial with resolution IV. Resolution IV means that main effects,each factor considered individually,are confounded with 3-way interactions. The PCB manufacturing processes selected as factors include laminate cooling rate,plating current density,pulse waveform,and hot air solder leveling (HASL) reflow. A confounded interaction cannot be separated out statistically from its “aliased” main effect. This DOE is a screening design,which is preferred for early investigation since the likelihood that a 3-way interaction would dominate over a main effect is extremely unlikely.
For this DOE,some deviations from an ideal experimentation setup are present. Since each coupon has multiple holes,samples are not uniquely independent. Also,the factors of pulse waveform and current density are not independent. The pulse waveform is also a nominal variable listed as a continuous factor for design purposes and has no center point value.

The electrochemical short,Conductive Anodic Filamentation,that that can develop within a PCB can be difficult to diagnose and detect,and there are many material and process issues that can lead to failure. Since the failure typically has a low incidence rate and typically occurs within multilayer boards identify the route-cause is challenging. NPL is developing a method for determining the sensitivity to various material and process factors that facilitate characterisation of these factors. Here we describe the first phase of the work where we have built a simple structure where we control the various materials and processes in building a PCB. In this simulation vehicle the resin,the glass fibres,the PTH characteristics are investigated,with various reflow processing to stress the structure. After damp heat testing with electrical bias CAF are formed,and since the simulation vehicle is thin it is easy to identify the CAF optically,in addition to the electrical measurements. The presented results will discuss the relative sensitivity to the material conditions and processing parameters within the simulation vehicle. For example the surface condition of glass fibres were found to be critical.

The Advanced Technology Center of the Lockheed Martin Corporation has developed a nanotechnology enabled copper-based electrical interconnect material that can be processed around 200 °C. The readily scalable Cu nanoparticles synthesis process uses a low cost solution-phase chemical reduction approach. A pilot plant is fully operational producing one lb per batch of nanomaterial. We have demonstrated assembly of fully functional LED test boards using a copper-nanoparticle paste with a consistency similar to standard solder. Further improvements have led to the assembly of a small camera board with a 48 pad CMOS sensor QFN chip and a 26 pin throughhole connector. In addition,we have a fully functional nanocopper assembly line in place for process development using standard industrial off-the shelf equipment. We are currently working with a commercial assembly house to dial-in the board assembly process. The fused material shows a tensile strength that is already in the range of space qualified solder. Once fully optimized,the nanocopper-based (trademarked CuantumFuseTM) solder-like material is expected to produce joints and interconnects with up to 10 times the electrical and thermal conductivity compared to tin-based solders currently in use and with a bond strength comparable or better than eutectic SnPb. Applications in space and commercial systems are currently under consideration.

While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease
of manufacture and the interconnection reliability are being reduced. This paper will introduce the use of embedded fibers in
the interconnections as a means of addressing these issues.
Flip chips bumps are evolving from large solder balls down to small thin copper pillars. Some copper pillars are solder capped and use a thermo-compression reflow attachment process. Smaller diameter copper pillars,while desirable by users,present a significant challenge to assemblers and reliability issues for end-users.
Nanostructures in the form of carbon nano-tubes have been evaluated for years. The recently created a means of growing metallic carbon nano-fibers,CNF's,to micro bumps which are solderable. When embedded with solder the fiber bumps produce robust component interconnections which can be less than 10 um in diameter and up to 20 um high. Attachment of the fiber micro bumps uses conventional thermo-compression bonding.
Results from the most recent evaluations will be presented indicating electrical performance and showing ease of manufacture resulting of such solder coated carbon nano-fiber micro bumps.

Nanomaterials have shown great promise in various applications including nanoelectronics and devices. However,in order to achieve large-scale nanoelectronics assembly and manufacturing,the development of smaller scale assembly and interconnection is necessary. More advanced nano-joining techniques are key enabling technologies in the construction of nanoelectronics and devices. In this presentation,we show that advanced nanosolder materials can be synthesized and developed for micro/nanoelectronics assembly and packaging applications. The nano-joining techniques are shown to be approached by utilizing nanosolders based on nanoparticles and nanowires. Both approaches are useful for the construction of different functional assemblies and nanodevices at the multi scales. The interactions between the nanosolders and substrates,including atomic diffusion,melting behavior and wetting property,are studied from both the one-dimensional and two-dimensional perspectives. The nano-joining techniques are also developed in consideration of the compatibility issue with the microelectronics assembly and packaging techniques.

The SMT industry’s one constant is change. Standards are continually updated and components are miniaturized for space savings. In addition to the changes that come,the industry is also faced with continuing to deal with areas that fail to change and update. A typical PCB manufacturer lays out a line based on the need to put solder paste on a PCB,place parts in the paste,and then reflow the product (Figure 1). The board size,typical components placed,and the required speed for the line are then considered. Eventually a SMT manufacturing line is purchased that can handle a large majority of the process needs. In almost all cases,there will be a component that cannot be handled by the automated process currently in use on the factory floor. This is not a problem that is caused by the engineer who specified the line,nor is it the chosen vendor’s false advertising. This problem plagues virtually all PCB manufacturers because it is not cost effective to purchase a specialty machine to handle a component that is expected to go away and not be used any more,or the component that is thru-hole and was expected to be replaced by a SMT component soon. Manufacturers are expected to build as demanded and very often that demand is outside of the specifications which they thought were adequate,but the quantity does not justify new special equipment. PCB manufacturers,for example,face the
challenge of placing very large connectors,whose size is outside the specifications of SMT machines (Figure 2). Some manufacturers use thru-hole components in products (Figure 3),yet not enough need for this exists to justify a thru-hole machine.
Infrequently used components may fail to justify standard packaging for use,and oddly shaped parts may simply be beyond
the scope of what a standard SMT machine can handle. In addition to the difficulty in managing the changes in size and type
of component for placement,manufacturers must also consider the cost effectiveness of any solution they devise for managing these “out of spec.” placement issues. Rarely do these issues justify the expense of purchasing a specialty machine. Rather,the manufacturer finds it more cost effective and more realistic to manage these processes with human resources. These manufacturing difficulties are not caused by poor engineering design,or by the chosen vendor’s inattentiveness to customer needs. At the end of the day,manufacturers have come to accept that they will purchase a SMT line for the
manufacturing floor that is capable of handling a large percentage of their process needs,but those out of specification parts
will always exist.

In the fast developing electronic industry the demands for production equipment are changing rapidly as well. The industry is looking for both,stable production processes and automated procedures in order to have full control of quality and costs.
This also affects the rework processes that are commonly still related to knowledge and skills of operators who are handling repair and touch-up of electronic assemblies.
To enable a rework system to carry out automated user independent rework the placement process needs to operate automatically. A new placement technology is introduced here that uses two cameras to identify the target area for component installation as well as the component pin structure. Image processing software calculates the correct placement position for the component out of the image information. A motorized four axes system is able to move the component to the target position without interaction of any operator. The procedure is based on an automatic pin detection algorithm along with a matching algorithm to find the correct position of the pin pattern in the target image. Several alignment procedures as well as camera corrections are implemented in order to reach the high demands of placement accuracy and repeatability.
The new placement technology relieves the user from exertive optical alignment and time consuming manual adjustment as well as guaranteeing a high repeatability in the positioning results. While the system is placing and installing the component the user can focus on preparative activities.
Besides automatic placement,the described rework technology allows automatic component flux and paste dipping as well as handling of paste printed components. Additionally soldering and desoldering processes are operated automatically.

As the Electronic Manufacturing Services (EMS) industry makes a push to bring manufacturing back to the United States it is clear that automation is necessary in order to keep prices competitive. The problem with automation in the EMS industry is the constant changing of designs and short life cycles of products. With hard automation the return on the investment (ROI) on many lines is not possible and therefore the manufacturing is kept offshore with manual processes. There is a solution to this problem which will change not only how automation and manufacturing is done in the United States but around the world as well. By using generic automation that can be used for the manufacturing of many products with little change over time and a small reinvestment it will completely change the decision to automate a line.
The vision for the future back end assembly manufacturing facility is similar to the current SMT assembly line. There will be different modules and stations that can be put together and programmed to do all the processes required by the particular assembly. Then with a simple rearrangement,program adjustment and incorporation of raw materials the line will be ready to perform a new assembly. This will allow manufacturing companies to bring products to market faster,an improved yield and with less of an initial investment. This paper will go into detail of an example of this type of line being deployed in Flextronics.

With the electronic industry moving towards lead-free assembly,traditional SnPb-compatible laminates need to be replaced with lead-free compatible laminates that can withstand the higher reflow temperature required by lead-free solders. Lead-free compatible laminates with improved heat resistance have been developed to meet this challenge but they are typically more brittle than SnPb laminates causing some to be more susceptible to pad cratering. In this paper,two novel approaches for minimizing pad cratering will be discussed. Preliminary results which validate the two approaches will also be presented.

Pad cratering test methods have been under development with the emergence of this laminate fracture defect mechanism. In additional to ball shear,ball pull,and pin pull testing methods,the acoustic emission method is being developed to evaluate
laminate materials’ resistance to pad cratering. Though the acoustic emission (AE) method has been proven to be able to detect pad cratering,no study has reported which AE parameters are good indicators for the susceptibility of PCB laminates to pad cratering. In this study,six different laminates subjected to three different pre-conditioning (multiple reflow) cycles have undergone the four-point bend testing. Four AE sensors were used to monitor pad cratering during the bend test. Several AE parameters including amplitude in dB level,the energy,and the location of each AE event under different load levels are recorded. Location analysis shows the majority of AE events are concentrated in the largest BGA package in the
test vehicle,which indicates that pad cratering is elevated with the larger size of BGA package due to high stress concentration. Both the number of AE events and the cumulative energy of AE events at a given applied load show that Laminate F is prone to pad cratering. However,there is no statistically significant difference in the lowest applied load to detectable AE among these six laminates. The ranking of the six laminate materials is different using different test methods. The most effective test method for predicting pad cratering susceptibility is inconclusive from this study.