High Power Transistors contain materials and structure that pose unique challenges to AXI technologies. The work discusses traditional AXI imaging and processing techniques and their limitations in very heavily shaded,and non-uniformly shaded situations. The work further discusses methods for voiding detection and presents a novel technique developed to overcome challenges presented by Copper Coin Power Transistors. Lastly the work presents considerations for optimal region size and data presentation to support testing to component-level voiding specifications.

C-mode scanning acoustic microscopy (C-SAM) is a non-destructive inspection technique showing the internal features of a specimen by ultrasound. The C-SAM is the preferred method for finding “air gaps” such as delamination,cracks,voids,and porosity. This paper presents evaluations performed on various advanced packages/assemblies especially flip-chip die version of ball grid array/column grid array (BGA/CGA) using C-SAM equipment. For comparison,representative x-ray images of the assemblies were also gathered to show key defect detection features of the two non-destructive techniques. Key images gathered and compared are:
•Compare the images of 2D x-ray and C-SAM for a plastic LGA assembly showing features that could be detected by either NDE technique. For this specific case,x-ray was a clear winner.
•Evaluate flip-chip CGA and FCBGA assemblies with and without heat sink by C-SAM. Evaluation was to evaluation defect condition of underfill and bump quality. Cross-sectional microscopy performed to compare defect features detected by C-SAM.
•Analyze a number of fine pitch PBGA assemblies by C-SAM to detect the internal features of the package assemblies and solder joint failure at either package or board levels.
•Twenty times touch up by solder iron having 700?F,each with 5-7seconds and induced defects were analyzed by C-SAM images.

Ceramics packages are being used in the electronics industry to operate the devices in harsh environments. In this paper we report a study on acoustic imaging technology for nondestructively inspecting underfill layers connecting organic interposers sandwiched between two ceramics substrates. First,we inspected the samples with transmission mode of scanning acoustic tomography (SAT) system,an inspection routine usually employed in assembly lines because of its simpler interpretation criteria: flawed region blocks the acoustic wave and appears darker. In this multilayer sample,this approach does not offer the crucial information at which layer of underfill has flaws. To resolve this issue,we use C-Mode Scanning in reflection mode to image layer by layer utilizing ultrasound frequencies from 15MHz to 120MHz. Although the sample is thick and contains at least 5 internal material interfaces,we are able to identify defective underfill layer interfaces.

Using modern laser systems for the depanelization of circuit boards can create some challenges for the production engineer when it is compared to traditional mechanical singulation methods. Understanding the effects of the laser energy to the substrate material properly is essential in order to take advantage of the technology without creating unintended side effects. This paper presents an in-depth analysis of the various laser system operating parameters that were performed to determine the resulting substrate material temperature changes. A theoretical model was developed and compared to actual measurements. The investigation includes how the temperature increase resulting from laser energy during depaneling affects the properties of the PCB substrate,which varies from no measurable change to a lowering of the surface resistance of the cut wall depending on the cutting parameters. In addition the amount and properties of the ejecta that are potentially resulting from the laser processing is investigated. Understanding the composition and quantity of any resulting residue may have a great impact to both the board design and the selection of the appropriate circuit board singulation method that will achieve the best possible results. An Energy Dispersive X-ray Analysis method (EDX) was performed to investigate if any unwanted material compounds are present on the cutting sidewalls of an FR4 circuit board substrate as a result of laser energy induced during the depaneling process.

Two new electroless copper baths have been developed to cope with upcoming miniaturization challenges in the high-end IC substrate segment as well as in the evolving HDI board market. The main challenge to be overcome is the reduction of the differential etch in the pattern plating process by decreased electroless copper thickness on the surface of the build-up layer. To this end,several requirements need to be fulfilled to ensure a safe and high yield production. First of all,the throwing power performance of E’less Copper IC and E’less Copper HDI especially in the wedges respectively at the bottom of the BMVs is crucial for the via-filling performance due to conductivity requirements. Two reliable throwing power measurement methods have been introduced and throwing power results presented in this paper show that the new electroless copper baths constantly achieve significantly better throwing power performance compared to the reference systems that are industry standards in the respective markets. A minimum target thickness of the electroless copper layer in the BMV (wedges) is therefore ensured while the thickness on the surface can be reduced for improved L/S resolution. Secondly,the adhesion of the copper layer on the bare laminate is a basic requirement for the high-end IC substrates manufacturing process. Favorable internal stress characteristics of the copper layer of the E’less Copper IC bath combined with excellent peel strength results ensure a reliable and strong adhesion of the copper layer on the resin surface. Thirdly,dry film adhesion and differential etching are key process steps for high yield manufacturing. The surface morphology of the E’less Copper IC layer enables improved mechanical anchoring of the dry film compared to the reference system and dry film adhesion data for E’less Copper HDI is under evaluation. Both electroless copper baths were thoroughly tested for industry standard reliability requirements and achieved excellent results.

Most of today’s printed circuit board base materials are anisotropic and it is not possible to use a simple method to measure thermal conductivity along the different axis,especially when a good accuracy is expected. Few base material suppliers’ datasheet show X,Y and Z thermal conductivities. In most cases,a single value is given,moreover determined with a generic methodology,and not necessarily adapted to the reality of glass-reinforced composites with a strong anisotropy. After reminding of the fundamentals in thermal science,this paper gives an overview of the state-of the art in terms of thermal conductivity measurement on PCB base materials,and some typical values. It finally proposes an innovative method called transient fin method,and associated test sample,to perform reliable and consistent in plane thermal conductivity measurement on anisotropic PCB base materials.

From the Apple Watch and body cameras for law enforcement to virtual reality hardware and autonomous transportation,the opportunities for electronics to improve our lives are limited only by our imaginations. The capability of existing PCB assembly technology needs to advance rapidly to meet the mission profile of these new devices. The demand common to all of these devices is increased functionality in a smaller space. For the solder paste manufacturer,this path inevitably leads to incorporating finer metal powder into solder paste to facilitate ultra-fine pitch printing. This study evaluates the benefits and implications of finer mesh solder powder on critical aspects of solder paste performance. Type 4,5 and 6 SAC305 solder pastes were tested and their characteristics in several key areas were measured and studied. The key input variables included powder size,effect of room temperature storage,pause time and PCB feature types. Output included print transfer efficiency,volume repeatability and performance stability over time. The goal of the study was to measure the benefits derived from smaller particle size and identify possible negative implications. With this information,assemblers and technical support personnel will better understand how to apply their resources to ensure the most robust process and optimized performance. The study was undertaken in two parts to measure both print characteristics and reflow characteristics. The print results are reported in this paper.

In the electronics industry,consumer demand drives a large portion of product innovations. Consumers want greater functionality and power,while maintaining a small footprint. Due to this demand,printed circuit board (PCB)manufacture and the related solder paste screen printing process become increasingly complex. Generally speaking,in high volume surface mount technology (SMT) assembly; consistent solder paste print volume and deposition are required to insure a high yield rate. With new product designs adopting finer pitch,smaller components,and greater density,stencil designs violating typical recommendations for area ratio are being evaluated. Using a stencil nearing or exceeding boundaries of known good performance challenges consistent screen print volumes and deposition throughout an entire PCB. This paper will review a solder paste developed for use with a combined solder paste inspection (SPI) and jetting tool. The paper will consider the viability of this process to prevent defects related to insufficient solder paste prints.

Water soluble lead-free solder paste is widely used in today’s SMT processes,but the industry is slowly moving away from water soluble solder pastes in favor of no-clean solder pastes. This shift in usage of solder paste is driven by an effort to eliminate the water wash process. Some components cannot tolerate water wash and elimination of water washing streamlines the SMT process. Despite this shift,certain applications lend themselves to the use of water soluble solder paste. High-reliability applications require removal of flux residues and it is much easier to remove water soluble flux residues than no-clean flux residues. Because of this reality,water soluble solder pastes will be used for the foreseeable future. Due to industry movement away from water soluble solder pastes,research and development resources have been focused on no-clean technologies. Some water soluble solder pastes in use today were developed many years ago,possibly before the era of lead-free soldering. Because of the prevailing trend toward no-clean formulation efforts,water soluble solder paste technology has fallen behind no-clean technology,especially for use with lead-free solder alloys. However in order to meet today’s requirements for certain applications,new high performance water soluble solder pastes are needed. This paper details the research and development of a new water soluble lead-free solder paste which improves on the performance characteristics of existing technologies. The key attributes of this solder paste are as follows:
• Environmentally stable in a wide range of conditions
• Long stencil life
• Excellent print characteristics
• Nominal wetting especially on hard to wet surfaces
• Very low solder balling and graping
• Easily removable flux residues
Challenging test methods were used to develop this solder paste and the results are detailed in this paper. Testing on this new water soluble solder paste is compared and contrasted to existing solder paste products. This development work created a new water soluble lead-free solder paste that meets the current and future needs of the industry.

As electronic assemblies continue to shrink in size,component population densities are increasing. Design engineers are forced to utilize all available board real estate and continuously push the limits of manufacturability. The next generation of board designs will incorporate even smaller passives than 01005 and tighter area array pitches than 0.3mm,while pushing design rules to reduce typical component spacing to less than 1mm. As limits are pushed,the need for advanced rework solutions is sure to increase from research organizations to volume manufacturing. This paper will address some of today’s most challenging rework applications and explore the demands of tomorrow including:
•Rework of 008004 micro passives
•LED rework as small as 0.5mm•Micro Sensor Rework
•Assembly of Delicate Beam Lead Diodes
•Flip chip
Specific challenges of reworking these applications will be identified and discussed,including process,material and equipment variables not common to 1mm plus rework.