The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods,with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired,testing a variety of laminate materials (standard volume production with UL approval,low loss,and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified,as well as possible correlations or relationships among these higher speed test methods.

How susceptible are the metals used in modern electronics manufacturing to corrosion by common beverages? This is a question of interest,especially to manufacturers,retailers and to a certain extent end customers. In this study the dissolution of aluminum,copper,gold,iron,lead,nickel,SAC305 solder,silver,tin and zinc was examined. Individual foils of these materials were fully immersed in one of sixteen chosen beverages and heated for 3 days at 40°C. The resulting solutions were analyzed using ICP-OES. The data were examined in light of the known pH,conductivity and ionic contents of the beverages,determined in previous work. Conclusions about the relative susceptibility to corrosion of the various metals and the corrosive power of the different beverages are made.

Particulate matter contamination is known to become wet and therefore ionically conductive and corrosive if the humidity in the environment rises above the deliquescence relative humidity (DRH) of the particulate matter. In wet condition,particulate matter can electrically bridge closely spaced features on printed circuit boards (PCBs),leading to their electrical failure. Failures attributed to particulate matter have even been observed in data centers where the gaseous contamination levels are low enough to meet the ANSI/ISA-71.04-2013 G1 severity level. The combination of miniaturization of electronic components,the reduction of feature spacing on PCBs and the loosening of the data center temperature and humidity envelope to save energy is making electronic hardware more prone to failure due to particulate matter. The characterization of particulate matter on PCBs is challenging because of the small amount of particulate matter available for analysis. The objective of this paper is to develop and describe a practical,routine means of measuring the DRH of minute quantities of particulate matter (1mg or less) found on PCBs. Data center particle filtration schemes and means of removing the particulate matter from PCBs will also be presented.

The demand for compute capability is growing rapidly fueling the ever rising consumption of power by data centers the worldwide. This growth in power consumption presents a challenge to data center total cost of ownership. Free-air cooling is one of the industrial trends in reducing power consumption,the power usage effectiveness (PUE) ratio,and the total cost of ownership (TCO). Free-air cooling is a viable approach in many parts of the world where the air is reasonably clean. In Eastern China,the poor quality of air,high in particle and gaseous contamination,is a major obstacle to free-air cooling. Servers exposed to outside air blowing in to data centers will corrode and fail at high rate. The poor reliability of hardware increase TCO dramatically. This paper describes a corrosion resistant server design suitable for reliable operation in a free-air cooling data center located in Eastern China where the indoor air quality can be as poor as ASHRAE (American Society of Heating,Refrigerating and Air-Conditioning Engineers) severity level G3. An accelerated corrosion test method of verifying hardware reliability in the ASHRAE severity level G3 environment is also described.

Due to the increasing demands placed on acid copper plating solutions to perform via fill plating of blind micro vias it is critical that the plating additives be monitored precisely. This paper presents electrochemical techniques for analyzing additives commonly used in via fill plating baths. The additives,commonly referred to as suppressor,brightener and leveler,all need to be precisely monitored during the production process in order to achieve optimum via fill. Utilizing cyclic voltametric stripping (CVS),these additive types can be monitored with a single analytical instrument when the proper techniques are employed and the measurement procedures are optimized for each additive.

This paper discusses a through hole copper filling process for application to high density interconnects constructions and IC substrates. The process consists two acid copper plating cycles. The first cycle uses periodic pulse reverse electroplating to form a bridge in the middle of the hole,followed by direct current electroplating to fill the resultant vias formed during the bridge cycle. This process can provide defect-free filled holes with total plated copper on the surface below 25 µm,with dimple less than 5 µm for boards with core thickness of 0.2 mm and 0.25 mm. This process was designed to be deployed in specially constructed vertical continuous platers (VCP),thus reducing capital equipment compared to horizontal conveyorized electroplaters. The chemical components,copper,acid and additive,for periodic pulse reverse plating cycle,are optimized via experimental conditions selected from DOE (design of experiments) software. Critical parameters are identified and the impact on cavity formation during the bridging step is quantified. The additive and copper concentrations play key roles in reducing defects during bridge formation and on the resultant via formation. A high performance via-filling process is used to fill the formed vias,with less than 5 micron dimple depth,while depositing approximately 12 microns on the surface. The thin surface copper enables fine line resolution without the need for planarization or grinding. The mechanical properties of the plated deposit meet or exceed all IPC standards. This process is applicable to both laser-drilled X shape through holes and mechanically drilled straight holes. Laser-drilled through holes are bridged faster than mechanically drilled holes. However,mechanically drilled holes show a lower tendency for drilling induced defects,especially at the smaller hole diameters of 0.1mm. This process has shown capability to fill through-holes in thicker cores of 0.4 mm to 0.8 mm,where further investigation continues.

This paper describes the results of a whisker formation study on SAC305 assemblies,evaluating the effects of cleanliness and lead-frame materials in room temperature/high humidity (25°C/85%RH). Cleaned and contaminated small outline transistors were soldered to custom designed test boards using Sn3Ag0.5Cu (SAC305) solder. Before assembly components were divided into two groups. The first group was cleaned using the method developed in this study. The level of contamination was 10 times below typical acceptable industry level and did not exceed 0.062 µg/cm2 (0.4 µg/in2) Cl. The second group was contaminated with NaCl. The piece part level of chlorine contamination 0.465 µg/cm2 (3 µg/in2) was selected to be within the industry levels encountered (no standards exist). After assembly,all the boards were cleaned,and half of them were re-contaminated to a level of at least 1.56 µg/cm2 Cl (10.1 µg/in2). Whisker length,diameter,and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets,where the thickness is less than 25 µm. The influence of lead-frame material,cleanliness,and environment on whisker characteristics is discussed. Assembly contamination is an important consideration for whisker growth in harsh service environments.

Packaging trends enable disruptive technologies. The miniaturization of components reduces the distance between conductive paths. Cleanliness of electronic hardware based on the service exposure of electrical equipment and controls can improve the reliability and cost effectiveness of the entire system. Problems resulting from leakage currents and electrochemical migration lead to unintended power disruption and intermittent performance problems due to corrosion issues. Solvent cleaning has a long history of use for cleaning electronic hardware. Limitations with solvent based cleaning agents due to environmental effects and the ability to clean new flux designs commonly used to join miniaturized components has limited the use of solvent cleaning processes for cleaning electronic hardware. To address these limitations,new solvent cleaning agents and processes have been designed to clean highly dense electronic hardware. The research study will evaluate the cleaning and electrical performance using the IPC B-52 Test Vehicle. Lead Free no-clean solder paste will be used to join the components to the test vehicle. Ion Chromatography and SIR values will be reported.

With regard to precision cleaning applications within electronics manufacturing,pH neutral product development was a major breakthrough in recent years. The impetus for this development resulted from changes with regard to solder paste formulations and resulting assembly processes. The greater use of lead-free solder paste and the required higher reflow profiles have resulted in even more difficult to remove burnt-in flux residues. Coupled with increases in component density,larger component packages,higher lead counts,finer lead spacing,and lower standoff distances,effective cleaning is greatly challenged. The aqueous alkaline based cleaning agents can effectively remove these flux residues,however,the process often requires an increase in wash temperature and exposure time,chemical concentration,and mechanical energy. Although an efficient and effective cleaning process can be developed,oftentimes,the required operating parameters present a new set of challenges with regard to material compatibility. Since their introduction,the newly developed pH neutral formulations have proven to be capable not only of removing these difficult post reflow residues from complex board geometries,but do so without affecting material compatibility of sensitive components. Additionally,they perform at low concentration levels. This study reviews the performance of pH neutral cleaning agents as compared to alkaline cleaning agent alternatives and includes field data demonstrating their effectiveness with regard to material compatibility and cleaning performance.

With the impending deadline for RoHS II and the elimination of exemptions for lead bearing solders in electronics for mission critical electronics,the issue of tin whiskers remains unresolved. Building on earlier data developed using unique test methods; the company is collaborating with universities in developing other methods of promoting whisker growth. In previous testing with specially prepared pure tin,these methods grow whiskers exponentially more quickly than the company bent wire method. The availability of new test methods would allow for dozens of alloy combinations to be tested more rapidly and in combination,thus accelerating the development of an alloy with a demonstrable benefit in reducing tin whisker formation and the attendant risks. In addition,this work has expanded the understanding of the growth mechanism for tin whiskers and what other mitigation strategies can be employed to reduce their propagation. Concurrent to test method development,the company has continued alloy development and has finalized several alloys that have demonstrated minimizing whisker formation when compared to widely used tin-silver-copper and tin-copper alloys. These novel alloys have also been developed within the context of manufacturability,regulatory restrictions and end user processes. These alloys meet the requirements of demonstrable reduction of tin whisker formation and would be ‘drop-in’ replacements for existing alloys.