To find defects of solder joint in printed wiring board assembly,quite a few test methods have been developed so far.
Capacitance method and IEEE 1149.1 or boundary scan method are often used to find opens between component leads and
pads on a printed wiring board. These methods,however,can find complete opens or complete shorts only. Latent defects that
can be complete defect after several years have not been found by the conversational method.
We have developed a method to find such latent defects by using 4-wire small resistance measurement technique and have
built in a flying-probe in-circuit tester. It measures the resistance between component leads and pads,and checks the volume
of the solder. Because the volume of the solder is inversely proportional to the resistance in-between,resistance measurement
can be a way to test the solderability.
This technique is industry proven. A lot of manufacturing plants which produce printed board assembly used in automotive
have adapted it. The printed wiring board assembly for automotive must endure vibration. Thus if a board assembly has a
latent defect,it can bring a serious accident. In my presentation,I would like to introduce the importance of SJIT,Solder Joint
Integrity Test,and a technique of SJIT.

This paper proposes an integrated design and test strategy which uses functional design blocks common to both designs and test fixtures,with the aim of saving time and money. Benefits of this strategy include reducing total product lifecycle cost by decreasing product and test development times,improving sustaining engineering processes,and reducing unique component counts across products and test fixtures.
Benefits and drawbacks to such a system are explored for a company that produces low volume,long life products. Benefits analysis is applied to software development and maintenance,schematic design,printed circuit board layout,hardware design,and fixture development for verification,qualification,and functional tests. A brief explanation is provided regarding how existing commercial functional test platforms can be inadequate in a low volume,long life integrated systems production environment. Analyses of process changes and technical hurdles that will need to be overcome while deploying such a system is examined. Finally,a phased approach is suggested that will minimize disruptions to daily operations; minimize any significant,up-front expenditure; and integrate into existing systems.

Complexity of test development for LED test and long LED test execution time in production are big challenges faced by the PCB manufacturing industry. This paper introduces a parallel multi-channel,multi-function color logical analysis (PMCMF-CLA) methodology to achieve zero additional test development and zero extra test execution time.
Traditional LED test includes two major tasks. 1. Development of test program to drive LED ON/OFF. 2. Test execution in production line. Test program development incurs a one-time cost for each type of DUT and it is a challenging job. The engineer needs knowledge of the device under test (DUT),and skills in test development. LED test execution contains several steps: driving LED on,waiting for LED to reach stable state,measuring LED,driving LED OFF. It would be ideal to save the effort of test development and time to run LED test in production.
In this case study,several PCB boards for desktop and laptop are studied. The number of LEDs varies from 0 to 20. The observation shows opportunity for zero additional test development. 70% to 80% of LEDs are lit at certain time during power-on test and functional test stage. Some LEDs are lit constantly. Some LEDs are turned ON or OFF according to time. The sampled ON and OFF forms a sequence of ON/OFF that provides information about not only whether LED is present,correct,and live,but also DUT functionality. This LED ON/OFF behavior presents an opportunity to have zero test development and zero extra test execution time.
PMCMF-CLA is a method to achieve LED coverage with zero additional LED ON/OFF test development and zero extra test execution time. PMCMF-CLA monitors multiple LEDs in parallel while other tests are running. Measurement of color (in the term of wavelength) and luminosity is recorded along with its sampled time. The sampled data forms color waveform that can be analyzed for various test purposes. For example,an expected LED has red color with certain luminosity. When it is detected in a color waveform,the information indicates the LED is present,correct and live. Color waveform analysis can be running in parallel while LED ON/OFF is monitored. Therefore,overall test execution time is almost the same as the test program that has no LED designated test.

Bottom Termination surface mount Components (BTC) are extremely popular because of their low cost,low stand-off height and excellent thermal and electrical properties. In this manufacturing arena,more and more connectors are utilizing the printed circuit board (PCB),due to its ability to allow convenient memory expansion in servers and embedded applications in communications. The challenge for the industry is to achieve the best possible BTC and connector solder joint quality. The following questions are keys to our discussion: What is the best way to use test and inspection techniques? How does one obtain accurate AXI (Automated X-ray Inspection) data and images for surface mount technology (SMT) process improvement? How does one minimize voiding in thermal pads caused by changing design rules in order to meet stringent customer requirements? How does one reduce the use of mechanical cross-sectioning,since it destroys costly PCBs and is time-consuming?
Identifying product defects associated with the manufacturing process is a critical part of electronics manufacturing. When faced with the need for high yields,especially for new product introduction (NPI),AXI faces challenges with new packages and processes,such as BTC and connectors. In this project,we will focus on how to use AXI to identify BTC and connectors,especially for voids from AXI testing of Mosfet and PQFN packages. The test methods include AXI,2DX and cross-section. We would like to reduce destructive methods in order to have a high-accuracy,low-void percentage from DOE (Design of Experiments).
We analyzed data from Tomosynthesis of AXI3 machine,AXI4 machine and 2DX,cross-section (virtual and horizontal cross-sectioning) using QFN package types (Mosfet and PQFN). The goal is to look for a correlation between AXI and 2DX,2DX and cross-section for improving accuracy levels with AXI data. The SMT process was improved,with good feedback of X-ray data and correlation results.

Bottom terminated components (BTC) are leadless components where terminations are protectively plated on the underside of the package. They are all slightly different and have different names,such as QFN (quad flat no lead),DFN (dual flat no lead),LGA (land grid array) and MLF (micro lead-frame. BTC assembly has increased rapidly in recent years. This type of package is attractive due to its low cost and good performance like improved signal speeds and enhanced thermal performance.
However,bottom terminated components do not have any leads to absorb the stress and strain on the solder joints. It relies on the correct amount of solder deposited during the assembly process for having a good solder joint quality and reliable reliability. Voiding is typically seen on the BTC solder joint,especially on the thermal pad of the component. Voiding creates a major concern on BTC component’s solder joint reliability. There is no current industry standard on the voiding criteria for bottom terminated component. The impact of voiding on solder joint reliability and the impact of voiding on the heat transfer characteristics at BTC component are not well understood. This paper will present some data to address these concerns. We will present our study on the thermal cycling reliability of bottom terminated components,including non-symmetrical LGA and QFN components. Two different solder process conditions and different voiding levels were included in the study,and the results will be discussed. The paper also covers our thermal modeling study of the heat transfer characteristic of BTC component.

The use of bottom terminated components (BTC) has become widespread,specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type,improved electrical and thermal performance relative to older packaging technology,and low cost make the QFN/BTC attractive for many applications.
Over the past 15 years,the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design,and must be given special attention to balance the dissimilar requirements.
The lack of leads on the QFN/BTC package and the low standoff height result in significantly less compliance relative to other package types,making the QFN/BTC package more susceptible to CTE mismatch issues. Careful assembly of QFNs and proper printed circuit board (PCB) design can result in acceptable reliability depending on the overall design. One area that has not been well addressed,however,is the impact of die to package size ratio,and how this factor should be considered in circuit card assembly. IPC-7093 mentions the inverse relationship between relative die size and reliability,and Syed and Kang found the relationship to be non-linear,yet die size is seldom noted in component datasheets,and vendor recommendations do not include this ratio as a factor in assembly.
In this study,the volume of solder used in assembly of two QFN/BTC packages will be varied to investigate the relationship between standoff height and thermal cycle life,and to determine acceptable process limits with respect to first-pass yields. The QFNs selected have dissimilar die to package size ratios to assess the impact of this factor on the process window. Solder joint defect levels and thermal cycle results will indicate the ability to adjust manufacturing parameters to achieve a balance between the two objectives of process yield and reliability. The results will define a process window that provides the optimal installation of these packages.

As channel speeds approach 25 Gbps,near the expected maximum bandwidth for traditional copper-based PCBs,every available tool to minimize total insertion loss in the board material system will need to be deployed. Material suppliers have devised low-Dk,low-loss dielectrics and fiberglass,as well as ultra-low-profile copper foils. However,one of the last remaining factors has not yet been quite so actively developed – the surface treatment applied by the PCB shop to the innerlayer cores prior to lamination.
In a previous paper presented at IPC,we described the effects of copper foil types,of varying levels of roughness,upon measured insertion loss of a stripline structure. We further showed the relative impact of different surface treatments (oxide and oxide alternative) which were then current in the industry. Recently,however,PCB chemical suppliers have begun offering new treatments targeted specifically at insertion loss and surface roughness minimization,whereas prior formulations were aimed at maximization of bond strength and prevention of pink-ring.
This paper builds upon our previous work by examining the insertion loss impact of such chemistry,holding constant the dielectric,test vehicle board design,and measurement technique used earlier. We are thus able to characterize the relative contribution of lower-roughness innerlayer treatment chemistry to loss reduction,as compared to conventional formulations.
1. Introduction and Background
2. Samples and Measurement Method
3. Measured Insertion Loss Results
4. Discussion and Opportunities for Further Work

This paper is an extension of an IPC paper [1] presented last year which addressed microwave insertion loss of common PCB transmission line circuits. Insertion loss of these circuits is made up of 4 components; conductor loss,dielectric loss,radiation loss and leakage loss. The previous paper focused on conductor loss and dielectric loss,whereas this paper will address radiation loss.
Radiation losses can be a disruptive force for many different reasons. Designs which are sensitive to EMI (ElectroMagnetic Interference) can be affected by radiation loss of a circuit and specifically how the radiated energy may corrupt neighboring circuits. Also the performance of loss-sensitive systems can be impacted with the addition of radiation loss when it is not fully considered. Finally,broadband high frequency RF and millimeter-wave applications certainly have issues with radiation loss and designers expend many efforts to account for these losses.

Nickel-palladium-gold-finished terminals are susceptible to creep corrosion. Excessive creep corrosion can result in device failure due to insulation resistance loss between adjacent terminals. The mixed flowing gas test has been demonstrated to produce creep corrosion on parts with nickel-palladium-gold finished terminals. Conformal coats are often used to protect printed wiring assemblies from failure due to moisture and corrosion. However,coating may not be sufficient to protect lead terminations from failure. In this study,acrylic,silicone,urethane,parylene,and atomic layer deposit (ALD) coatings were examined for their effectiveness at preventing corrosion of nickel-palladium-gold-finished terminals. The coverage of each coating was examined,and assemblies were subjected to eight hours of mixed flowing gas as well as temperature cycling. Non-uniform coating thickness was observed in the areas of the terminals. On some areas,little to no coating material was found for the acrylic,silicone,and urethane coatings. Parylene,which had the most uniform coating,was found to provide the best resistance to corrosion,while corrosion products were observed on the terminals of inspected parts protected by the other coatings.

The iNEMI technical subcommittee on creep corrosion is developing a flowers-of-sulfur (FOS) based qualification test for creep corrosion on printed-circuit boards (PCBs). The test setup consists of a 300-mm cube chamber with two means of mounting the test specimens and flowing air over them to expose them to constant,predefined humidity and temperature conditions and sulfur and other contaminants. The FOS chamber performance has been evaluated using copper and silver foils and preliminary test runs have been conducted on PCBs from a manufacturing lot known to have failed in service. The effect of air velocity on the copper and silver corrosion rates was quite linear. The effect of humidity on copper and silver corrosion rates in the low air velocity range of less than 0.1 m/s showed a strong dependence on relative humidity. In the high velocity range of 1 m/s,there was no clear dependence of humidity on copper and silver corrosion rates. A means has been developed for applying controlled concentration of ionic contamination on selected local areas of test PCBs. Preliminary test runs have shown that ionic contamination found in fine dust may be a necessary condition for copper creep corrosion. Printed circuit boards from a manufacturing lot that suffered creep corrosion in service,with and without dust contamination applied to them,were tested in a FOS chamber at 60oC with 1 m/s air flowing over them. The PCBs with no dust contamination did not suffer creep corrosion in the 3-day test; whereas,the PCBs with dust contamination suffered creep corrosion with morphology similar to that occurring in the field.