Materials Registry for Printed Electronics
- WMU’s CAPE received an award from FlexTech Alliance to create an online database for accessing technical information on functional materials used in manufacture of printed and flexible electronics.
- Purpose:
- Provide increased access to technical information about available products – both research and commercial
- Facilitate greater visibility of material suppliers within the printed and flexible electronics supply chain.
- Strengthen printed electronics industrysupply chain

Manufacturing technology faces challenges with new packages/process when confronting the need for high yields. Identifying product defects associated with the manufacturing process is a critical part of electronics manufacturing. In this project,we focus on how to use AXI to identify BGA Head-in-Pillow (HIP),which is challenging for AXI testing. Our goal is to help us understand the capabilities of current AXI machines.
For the study we used two boards exhibiting HIP defects with four types of AXI machines at four sites in Flextronics manufacturing,or vendor laboratory. The AXI machines used have different X-ray technologies: Laminography and Tomosynthesis. We collected three sets of data with AXI 1 machine (Laminography),and AXI 4 machines (Tomosynthesis); one set of data with AXI2 (Tomosynthesis); and 4 sets data for AXI3 (Tomosynthesis). We studied AXI measurement data with the different AXI Algorithm Threshold settings. The data indicated clearly that the Algorithm Threshold settings are very critical for detecting HIP,including open. The defective HIP pins are validated by using 2DX and CT scan.
The test data consist of Defects Escaped %,False call PPM and also Gage R & R. The AXI images for HIP pins,false call pins and defects escaped pins are presented in the paper. The 2DX and CT images are provided for identifying HIP type (shape and size).

SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller,with denser interconnect arrays,and processes such package-on-package assembly become prevalent,advanced methods using dual surface full-field data become critical for effective Assembly Planning,Quality Assurance,and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required,to effectively address the challenges of modern SMT assembly.
To fully understand and characterize variation in the gap that is the main cause of solder joint defects such as head-in-pillow,shorts,and opens,analysis of the interface between the mating surfaces needs to be:
• Full-field: A high density of data represents surface warpage much more finely than an approximation such as coplanarity,allowing area-specific review and analysis
• Dual-surface: Making assumptions about how the “bottom” surface is shaped when mounting a component neglects the complex behavior the land area might exhibit during the thermal cycle,and is a deficiency when attempting thorough assembly planning or failure analysis
• Full-profile: Making assumptions about when the single temperature when warpage of surfaces is important during the thermal cycle can lead to missing critical parts of the reflow process,overlooking when defects such as head-in-pillow can be caused
• Statistical: A large enough quantity of samples should be measured to allow confident calculation of expected average,maximum,minimum,and extreme (3s) gaps between surfaces. After measuring warpage of multiple surface mount components and land areas separately,the collected data can be combined into statistical summaries for each temperature point.
Reviewing the combined data at the start of assembly planning can provide an overview of dual-surface warpage at each temperature,and for the entire thermal profile. The measurement and analysis results that follow include a package-to-board assembly interface case study,and calculations,graphs,and methodology highlighting the use of gap limits and pass/fail maps to visualize areas with potential assembly issues.
This analysis method provides new capabilities when planning and monitoring the assembly interface across a full reflow cycle that can help predict and compensate for defects such as head-in-pillow.

The high speed transmission applications in the electronic product become inevitable developing trend. The signal integrity becomes the most important issue in the electronic industry. The material suppliers,PCB manufactures,OEM designer commonly face the serious issue “how to keep signal integrity operated in the high speed transmission” for the modern electronic application nowadays.

The material suppliers dedicated into developing lower dielectric constant and dissipation factor material,PCB manufactures define the low loss material and copper foil selection guide and more delicate process handling. The OEM specify the signal integrity form the insertion loss and extracted material Dk / Df from signal loss result . All of these are for keeping signal could be transmitted completely at higher bandwidth. We discuss the following factors affect insertion loss result in this paper,such as material Dk / Df,copper foil type,skin effect,impedance variation,line width,line space,black / brown oxide treatment,dielectric thickness,via stub effect and so on through TDR and VNA measurement and simulation analysis result .

We hope we could more understand the mystery of signal loss issue through these discussions and meet the signal loss specification from the OEM designer.

Throughout a product’s life cycle it may need to be tested various times. New product designs need to be validated during the prototyping phase,manufacturing defects need to be detected and diagnosed during the production phase,and products may need to be tested and/or updated while they are in use at the end customer,while defective units returned from the field need to be retested. This paper discusses different test access methodologies and elaborates on Embedded System Access (ESA) strategies in particular,with examples for its use in practice.

The growing transmission speed and volume of digital content increases the pressure on reduction of overall insertion loss of printed circuit boards permanently.
In today’s circuit boards,it is not only the transmission line itself,but also the via structure that impacts the insertion loss profile. To optimize the via,the stub length needs to be reduced by methods like backdrilling the copper out of the unused portion of the PTH.
In this paper,the influence of remaining stub lengths – varied between a couple of mils and 100mils - on the insertion loss profile is evaluated. As a second variable the size of the antipad is chosen and a two factor,multiple level DOE is performed.
Both,single ended and differential insertion loss is investigated and an ‘analysis of variance’ approach is used to determine the level of influence of the variables stub length and antipad size at various frequencies up to 40GHz.
The frequency of the quarter-wave-length-resonance is correlated to the stub length as well as the increase of the insertion loss well below the resonance point is discussed.
The paper describes the test vehicle,the performed measurements and discusses the electrical performance characteristics of the various test cells. A recommendation for an acceptable stub length is given.

Printed Circuit Boards (PCB’s) have been used for many years in low loss,high frequency microwave applications and many of these circuits have become increasingly complex. Often these complex circuits are just combinations of much simpler microwave PCB constructions and understanding the basic structures can be very advantageous for the PCB designer and fabricator. Each of these microwave structures have different loss mechanisms and this paper will focus on the three most common microwave PCB structures and their loss properties. The three structures are: microstrip,coplanar and stripline. Initially a basic overview of relative electromagnetic concepts will be given and following will be comparisons regarding loss performance of the different structures,using electromagnetic modeling software and measured data.

Importance of the properties during curing:
- Curing analysis has to be carried in a PCB level to improve understanding warpage mechanism. Specially it is very important in a laminating process due to cure shrinkage of PPG as a function of degree of cure.
- Therefore,it is strongly demanded that curing properties should be measured in material maker.
Embedding Material Combination:
- Large deformation at the embedding resin layer is more effective to reduce warpage of the embedded package.

Embedded Passive Technology is a viable technology that has been reliably used in the defense and aerospace industry for over 20 years. Embedded Passive (Resistors and Capacitors) Technology have a great potential for high frequency and high density applications. It also provides better signal performance,reduced parasitic and cross talk. This paper summarizes the selection of resistor embedded materials,evaluations of resistive material (Phase 1) and duplication of a complex digital design (Phase 2). Phase 1 –resistive materials (Foil 25O/sq NiCr and 1kO/sq CrSiO) and resistive-Ply materials (25O/sq and 250O/sq NiP) were chosen for evaluation.
Phase 2 – Due to the high level of complexity and advance materials dielectric,the Digital Imaging Processor unit was chosen as an evaluation vehicle. Process Evaluation for embedded was used to determine present process gaps for laser trimming,fabrication material,raw board test and defining specifications for DFM and layout design.

Embedded components technology has launched its implementation in volume products demanding for highest miniaturization level. Small modules with embedded dies and passive components on the top side are mounted in hand held devices. Smart phones are the enablers for this new technology using the capabilities of embedded components. These modules have already shown a high level of reliability which has been a pre-requisite to get acceptance for volume products. Embedded dies are relative small with dimensions of about two by two millimeter and therefore all critical topics like the CTE mismatch of components and PCB materials,process die attachment are on a non-critical level. The roadmaps for the application development show a drastic increase of the complexity of the modules and in parallel increasing I/O numbers and die dimensions. Applications in the development pipeline show already die dimensions of seven by seven millimeter.
Based on this development roadmap a simulation project was started with the Material Center Leoben and Thales Global Services to evaluate the stress situation of embedded components and to build a thermo mechanical simulation model. The verification of this model was started by characterization of silicon dies and embedding of standardized components into PCB to get detailed stress parameters for these components. The next step of simulation deals with the simulation of embedding processes. Die assembly is the first process followed by the lamination process to form the embedded core. For the assembly process a DOE has been done to correlate the results with the simulation model.
All along the European funded FP7 HERMES*project huge efforts have been deployed in order to characterize the reliability of active and passive embedded chips,as well as packages assembled on the outer layers of the PCB . To achieve a high level of reliability of future complex modules using HERMES technology,work has been done to address different aspects like process optimization including different build-ups,best choice of base material,different size of active dice and design rules,knowledge of failure mode.
HERMES was successful closed in February 2012 and the final results of the HERMES embedding technology are shown in this paper. A dedicated test vehicle using a 4 (level of stacked µvia) +core +4 simulating a functional demonstrator have been manufactured and stressed under accelerated thermal cycling in the range -40°C/+125°C and under continuous monitoring.
This test vehicle includes embedded chips of different sizes,passive chips and BGA/QFN package assemblies on the external faces of the PCB. The design permits to isolate component (in daisy chain) and interconnections to facilitate the reliability and failure analysis. A detailed construction analysis of the manufactured boards has been done before to start the reliability test in order to have a reference.