This paper discusses a through hole copper filling process for application to high density interconnects constructions and IC substrates. The process consists two acid copper plating cycles. The first cycle uses periodic pulse reverse electroplating to form a bridge in the middle of the hole,followed by direct current electroplating to fill the resultant vias formed during the bridge cycle. This process can provide defect-free filled holes with total plated copper on the surface below 25 µm,with dimple less than 5 µm for boards with core thickness of 0.2 mm and 0.25 mm. This process was designed to be deployed in specially constructed vertical continuous platers (VCP),thus reducing capital equipment compared to horizontal conveyorized electroplaters. The chemical components,copper,acid and additive,for periodic pulse reverse plating cycle,are optimized via experimental conditions selected from DOE (design of experiments) software. Critical parameters are identified and the impact on cavity formation during the bridging step is quantified. The additive and copper concentrations play key roles in reducing defects during bridge formation and on the resultant via formation. A high performance via-filling process is used to fill the formed vias,with less than 5 micron dimple depth,while depositing approximately 12 microns on the surface. The thin surface copper enables fine line resolution without the need for planarization or grinding. The mechanical properties of the plated deposit meet or exceed all IPC standards. This process is applicable to both laser-drilled X shape through holes and mechanically drilled straight holes. Laser-drilled through holes are bridged faster than mechanically drilled holes. However,mechanically drilled holes show a lower tendency for drilling induced defects,especially at the smaller hole diameters of 0.1mm. This process has shown capability to fill through-holes in thicker cores of 0.4 mm to 0.8 mm,where further investigation continues.

This paper describes the results of a whisker formation study on SAC305 assemblies,evaluating the effects of cleanliness and lead-frame materials in room temperature/high humidity (25°C/85%RH). Cleaned and contaminated small outline transistors were soldered to custom designed test boards using Sn3Ag0.5Cu (SAC305) solder. Before assembly components were divided into two groups. The first group was cleaned using the method developed in this study. The level of contamination was 10 times below typical acceptable industry level and did not exceed 0.062 µg/cm2 (0.4 µg/in2) Cl. The second group was contaminated with NaCl. The piece part level of chlorine contamination 0.465 µg/cm2 (3 µg/in2) was selected to be within the industry levels encountered (no standards exist). After assembly,all the boards were cleaned,and half of them were re-contaminated to a level of at least 1.56 µg/cm2 Cl (10.1 µg/in2). Whisker length,diameter,and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets,where the thickness is less than 25 µm. The influence of lead-frame material,cleanliness,and environment on whisker characteristics is discussed. Assembly contamination is an important consideration for whisker growth in harsh service environments.

Packaging trends enable disruptive technologies. The miniaturization of components reduces the distance between conductive paths. Cleanliness of electronic hardware based on the service exposure of electrical equipment and controls can improve the reliability and cost effectiveness of the entire system. Problems resulting from leakage currents and electrochemical migration lead to unintended power disruption and intermittent performance problems due to corrosion issues. Solvent cleaning has a long history of use for cleaning electronic hardware. Limitations with solvent based cleaning agents due to environmental effects and the ability to clean new flux designs commonly used to join miniaturized components has limited the use of solvent cleaning processes for cleaning electronic hardware. To address these limitations,new solvent cleaning agents and processes have been designed to clean highly dense electronic hardware. The research study will evaluate the cleaning and electrical performance using the IPC B-52 Test Vehicle. Lead Free no-clean solder paste will be used to join the components to the test vehicle. Ion Chromatography and SIR values will be reported.

With regard to precision cleaning applications within electronics manufacturing,pH neutral product development was a major breakthrough in recent years. The impetus for this development resulted from changes with regard to solder paste formulations and resulting assembly processes. The greater use of lead-free solder paste and the required higher reflow profiles have resulted in even more difficult to remove burnt-in flux residues. Coupled with increases in component density,larger component packages,higher lead counts,finer lead spacing,and lower standoff distances,effective cleaning is greatly challenged. The aqueous alkaline based cleaning agents can effectively remove these flux residues,however,the process often requires an increase in wash temperature and exposure time,chemical concentration,and mechanical energy. Although an efficient and effective cleaning process can be developed,oftentimes,the required operating parameters present a new set of challenges with regard to material compatibility. Since their introduction,the newly developed pH neutral formulations have proven to be capable not only of removing these difficult post reflow residues from complex board geometries,but do so without affecting material compatibility of sensitive components. Additionally,they perform at low concentration levels. This study reviews the performance of pH neutral cleaning agents as compared to alkaline cleaning agent alternatives and includes field data demonstrating their effectiveness with regard to material compatibility and cleaning performance.

With the impending deadline for RoHS II and the elimination of exemptions for lead bearing solders in electronics for mission critical electronics,the issue of tin whiskers remains unresolved. Building on earlier data developed using unique test methods; the company is collaborating with universities in developing other methods of promoting whisker growth. In previous testing with specially prepared pure tin,these methods grow whiskers exponentially more quickly than the company bent wire method. The availability of new test methods would allow for dozens of alloy combinations to be tested more rapidly and in combination,thus accelerating the development of an alloy with a demonstrable benefit in reducing tin whisker formation and the attendant risks. In addition,this work has expanded the understanding of the growth mechanism for tin whiskers and what other mitigation strategies can be employed to reduce their propagation. Concurrent to test method development,the company has continued alloy development and has finalized several alloys that have demonstrated minimizing whisker formation when compared to widely used tin-silver-copper and tin-copper alloys. These novel alloys have also been developed within the context of manufacturability,regulatory restrictions and end user processes. These alloys meet the requirements of demonstrable reduction of tin whisker formation and would be ‘drop-in’ replacements for existing alloys.

The change to lead-free solders in electronic assemblies created a need to replace tin-lead solderable termination finishes with materials such as pure tin or soft gold,on electronic components and substrates. Gold presented a risk of solder joint embrittlement,which could reduce the joint mechanical durability. Several case studies were run,because solder joint embrittlement prevention requires a clear understanding of the materials and mechanisms of embrittlement. We confirmed two known mechanisms and verified two other ways in which gold finishes can degrade solder joints. The known mechanisms are,1) A gold layer dissolves from one side of a surface mount joint and precipitates AuSn4 compound onto the opposing termination and 2) The gold fully dissolves from a surface mount termination,but it results in an excessive gold weight percentage in the joint. The other ways are,3) A manual soldering process temperature is high enough to dissolve some nickel along with the gold and 4) A slow dissolving,hard gold surface finish incompletely dissolves during plated-through-hole soldering and solid state diffusion forms an AuSn2 compound layer. Close-up and cross-sectional images with SEM/EDS compositional information are shown for each case. A table of solder and gold volumes,which produce 3.0 and 4.0 weight percent gold,is provided. The embrittlement problems and their reliability solutions are discussed (over twenty literature references). The data suggests how to improve gold plating requirements,for solder joint embrittlement prevention,in solder assembly industry standards.

There is considerable interest in finding and replacing lead based solder alloys in high power environments and for existing high temperature operating environments. The high power electronics market requires alloys that do not contain lead but perform equally as well. With the increasing temperature requirements for harsh electronics in automotive and drilling applications the temperature these products require are increasing from 150 C to 200 C and equally need to consider alternatives. This project compared solder joints consisting of existing lead-free and leaded solders produced with laser and robotic iron soldering on polyimide substrates. The soldering of through-hole connectors was used to examine the changes that take place during high temperature storage of different solder alloys. This part of the work was aimed at the existing high temperature organic level assembly market or those companies moving into that product environment. There currently is a dearth of published data in this area. The work reported here can be compared to sintered silver joining trials reported elsewhere. Flux residues were considered in this work,particularly those from cored wire,where spitting and solder balling can be an issue. Robotic and laser soldering can achieve rapid heating of the solder with undesirable spitting of the flux as the result. We looked at the various approaches to solving this problem.

Printed Circuit Boards (PCBs) and Printed Electronics (PE) both describe conductor/substrate combinations that makeconnections. Both PCB and PE technologies have been in use for a long time in one form or another with PCBs currently the standard for complex,high speed electronics and PE for user interface,complex form factor or other film based applications. New and innovative applications create the opportunity for promising structures. Taking advantage of the PCB shop’s capability as well as the material set can help create these structures and indeed PE materials can find use in more traditional PCBs. New materials and new uses of existing materials open up many possibilities in electronic interconnecting structures. PCB manufacturers have a complex manufacturing infrastructure,well suited for both additive and subtractive conductor processing. While built around rigid material processing (flex PCB being the exception),there are opportunities for PE substrate processing. As electronics devices are applied to more and more parts of our lives,we need to continually push for better solutions. Fit,function,manufacturability,and cost are all important considerations. Crossing the PCB/PE boundary is a way to meet the challenge.

This paper discusses a nano copper based paste for use in via filling. The company manufactures nano copper and disperses the coated nano copper into a paste in combination with micron copper. The resultant paste is injected or fills a via. The via is subsequently sintered by means of photonic sintering,or by heat in a reducing environment. The process will be accomplished in under an hour and results in filled solid copper vias.

This paper documents the experimental work performed to further understand the impact on mid-chip solder balling from both the manufacturing process and the flux chemistry. Mid-chip solder balling is a defect typically associated with solder paste exhibiting poor hot slump and/or insufficient wetting during the reflow soldering process,resulting in paste flowing under the component or onto the solder resist. Once molten,this solder is compressed and forced to the side of the component,causing mid-chip solder balling. To increase the understanding of what factors can impact mid-chip balling,a study was undertaken to examine the effects of process variants and flux chemistry. Stencil thickness,aperture size and aperture shape were all identified as potentially significant factors with regards to process influence. Testing also revealed that the volume of paste was not necessarily proportional to the number of mid-chip balls,but was more influenced by the position of the paste relative to the pad. Comparative testing of a range of flux chemistries indicated that this also had a substantial effect on mid-chip ball occurrence. The data suggested that mid-chip balling could be controlled by both process and flux design. New methods of quantifying the severity of mid-chip solder balling are currently being investigated.