Typical SMT production lines are a collection of disconnected machines performing various tasks. Errors can occur at any step during this process,but often go undetected until the PWB is completed and soldered and it is too late to do anything other than re-work or scrap it. New tools with better integration are required to support the demand for increased yields and improved efficiency.
To prevent defects from simply passing from one machine on to the next,it is necessary to have inspections throughout the line. Better yet,sensing at different points should be linked to form a complete solution. This is especially critical in the placement phase of assembly due to the wide variety of inputs (components) and movements. The assembly system has to take up to hundreds of different components and individually place them at different locations on the PCB. This complicated task requires more thorough oversight to ensure defects are not created or passed on. Optical sensors can provide this oversight into the assembly process and offer the benefits of being fast,accurate,and non-contact.
Some of the challenges of integrating these sensing technologies are cost and space. It would be too expensive to have a complete inspection machine before and after each assembly system and take up far too much space. New generations of optical sensors,however,are also compact enough such that they can be embedded at key locations within the PCB assembly process. These sensors can be integrated to form a complete web of error prevention.
This paper discusses the new integrated optical sensing technologies that make it possible to virtually guarantee that only good PCBs will pass through the assembly process,reducing costly rework or scrapped PCBs and improving efficiency.

A PCB fails final test. Why? Was it the solder paste? The screen printer? The PCB assembly machine? The reflow oven or none of the above?
Unplanned downtime is a costly fact of life. In order to minimize the length of downtime it is necessary to have clear details on exactly what the source of the problem is,not just the symptoms. This information allows operators and maintenance personnel to go directly to take corrective steps more quickly and minimize downtime.
There are many machines and materials involved in the assembly of a complete PCB; screen printers,conveyors,pick and place systems,reflow ovens,Automated Optical Inspection (AOI),solder paste and components. Some of this equipment has the ability to check its results before,during or immediately after it has completed its task.
Until now there have been few real-time tools for the pick and place systems. In many cases,high speed movement on these machines makes it extremely hard to “see” exactly what is happening. Components misplaced by the assembly system could be caused by many different factors. Without tools to provide a clear view of very high speed placement,it is difficult to the cause of misplacement.
How much easier would this task be if operators and maintenance personnel are armed with detailed information on the nozzles,feeders,and actual images of the picking and placing of parts on the PCB?
This paper will discuss tools available for the placement machine to assist in root cause failure analysis (RCFA).

3D is the shorthand term for the three dimensions of Cartesian coordinate space X,Y and Z. With that definition in mind,one will find with little or no stretching of the imagination,that the first electrical interconnections,performed using discrete wires were unquestionably 3D. If one doubts it they can look at almost any electrical product from the time of the 19th century telegraph onward. 3D interconnections are found virtually everywhere. It is really 2D that is more illusive if one thinks about it. Even so,3D interconnection solutions and options have dominated the electronics manufacturing industry's attention over the last few years and interest in the topic has been accelerating. The reasons for this interest are manifold but the root cause is that the third dimension provides the ability to extend the pursuit of ever greater density when the acknowledged physics based limits that will ultimately spell the end of Moore's Law kick in. In order to keep delivering the promise of better cost/performance metrics for each new generation of electronics,interconnection technologies which take advantage of the third dimension will play an increasing important role in the future. In fact electronic interconnection
technologies will undoubtedly pace price and performance improvements for most if not all future electronic products and 3D
interconnections will play a pivotal role. This paper discusses 3D solutions which have been used from past to present from chip to system and will included a glimpse of what might be ahead.

After the implementation of RoHS and the discontinued use of lead bearing products and the introduction of lead free (LF)
solders,tin and its alloys have come to the forefront as the first choice of replacement to tin-lead.
On the solder side the transition has moved forward and solutions have been implemented,like the SAC family of LF solders
for paste reflow and tin-copper for HASL (hot air solder leveling). The industry is constantly making progress adapting its
materials and processes to the higher reflow temperature profile for these LF solders. Today there is a much better
understanding of the types of solder joints that are formed; their reliability and the type of intermetallic compound (IMC)
formed.
On the surface finish side,replacing tin-lead has posed greater challenges. Component leads and connector finishes were
being converted to tin as an obvious alternative. This works well as a soldering surface,however any part of the lead or the
connection surface that is not soldered to,has shown a potential to form tin whiskers over the life of the part. Internal stresses
in the deposit due to IMC formation or external stresses on the deposit are known to initiate whisker formation.
In this paper two approaches are implemented to dissipate the stress that is formed,the first is to modify the substrate surface
to control the growth in thickness and direction of propagation of the IMC and the second is to modify the large columnar tin
deposit crystal structure to mimic the fine equiaxed structure of tin-lead solder. The former is achieved thru controlled micro
roughening of the substrate and the latter by the use of additives to the plating bath.
Data will be presented to show the effect of each of the two approaches on the dissipation of the stress,resulting from IMC
formation. As the stress is dissipated the primary cause of whisker formation is eliminated.

In recent years the PCB industry has increasingly turned to digital,or maskless,imaging techniques in order meet demands for tighter registration between layers. Many of these techniques,including laser direct imaging (LDI),rely on a “dot-matrix” style exposure technique that uses “binary” pixels and small pixel or dot spacing to achieve the required resolution. This results in limitations in write speed and throughput,since many small pixels or dots must be written over a relatively large area PCB substrate. A patented gray level technique1 based on a commercially available digital micro-mirror device (DMD) achieves required resolutions with a relatively large projected pixel size,and thus offers a higher speed alternative to conventional digital techniques. Gray level,or dose control as a function of panel position can also provide some degree of compensation for minor processing or development artifacts that are known to recur in the same areas of a panel.

•Background and Objective
•Head-in-Pillow (HiP) Defect
•In Circuit Test (ICT) Testability
•Evaluation Steps
- Solder Paste Selection
- Head-in-Pillow Test
- Printability & Solderability Tests
- Surface Insulation Resistance (SIR),Electrochemical Migration (ECM) & Ion Chromatography (IC) Tests
- Verification Build

•Overview
•Test Method Considerations
•Proposed Test Methodology
•PCB,Stencil & Part Information
•Pick-up Adapter Design
•Test Setup Overview
•Head-in-Pillow Defect Detection
•Test Parameters
•Thermal Profile Comparison
•Test Results Classification
•SnPb & Pb-free Solder Paste Testing Results
•Influence of Flux Dip

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As technology becomes increasingly reliant on electronics,understanding the longevity of lead-free solder also becomes imperative. This research project focused on phase transformation kinetics within SAC 305 lead free solder during thermal aging processes. Today in the electronics industry,it is the most widely used solder,making it a high priority to understand its long-term stability and performance in a variety of service conditions. Reaction kinetics during thermal aging has being studied to parallel a previous research project concerning the activation energy to form Cu3Sn1. Results from the previous project will be included for the purpose of comparison.
The previous research project was designed to determine which application parameters will immediately cause the growth of the detrimental Cu3Sn1 layer. The data was useful in predicting the amount of growth within this layer during soldering. The current research has analyzed the effect of various aging temperatures on the initial growth of Cu3Sn1.

Although many predicted the demise of through-hole components,they are alive and well with tens of billions used each year. In mixed SMT/through-hole PCBs,through-hole components,and especially connectors,are often used for their mechanical robustness. A typical example would be a USB connector in a laptop PC. Typically an SMT connection just doesn’t have the mechanical robustness needed to support multiple connector plug-in and removals. However,performing a full wave soldering process to assemble a few through-hole components on a mostly SMT PCB doesn’t usually make economic sense and may damage the PCB. In such situations,the best option is often to assemble the through-hole components and connectors with a selective soldering process.
This paper touches on identifying favorable flux properties,down-selecting low solids fluxes for lead-free selective wave soldering,the selective soldering process itself,and testing criteria. Topics reviewed will be the flux selection,optimizing the selective soldering process by varying the flux concentration,pre-heat parameters,soldering temperatures,and dwell time. The paper will finish with a summary of the work and a systematic process to select a flux and optimize the selective soldering process for high yields and quality.