The reliability of an embedded planar capacitor laminate under a variety of environmental stress and bias conditions was investigated. The dielectric consisted of a composite of BaTiO3 particles in a bisphenol-epoxy matrix. The capacitor laminate was embedded in a 4-layer test board in which the power plane was etched to form discrete embedded capacitors having a common ground plane. Capacitors of two different areas were studied,having capacitances of about 400 pF and 5 nF.
The test vehicle with embedded capacitors was subjected to temperature and voltage aging and temperature-humidity-bias
(THB) tests at different stress levels. Three parameters,capacitance (C),dissipation factor (DF),and insulation resistance (IR),were measured in-situ during stress testing. Results are presented of testing at multiple stress levels in temperature and voltage aging tests and THB testing. Changes in electrical parameters during stress testing are reported,as well as the effects of stress conditions and levels on characteristic life. Physical analysis is used to identify the material response of the embedded capacitor laminate to the imposed stresses,providing the basis for recommendations regarding laminate design and usage.

Pad cratering in the PCB is a new failure mode encountered in electronic assemblies,particularly in lead-free products. The
failure mechanisms and root causes are not yet fully understood,and lack appropriate industry standard tests for PCB qualification with regard to pad cratering. This paper reviews major publications and research reports on various PCB materials from industry studies in this field. Various PCB tests,such as flexural strength test and pad strength test,have been studied. It is recommended that the qualification of the PCB can be done in two stages: PCB board level and PCBA product level. From those results,a new qualification method is suggested for screening out PCB pad cratering failures.

The mechanical behavior of printed circuit assemblies (PCA) at high strain rates is very important for the reliability of products used in harsh environments. The transition to Pb-free materials in the general electronics industry significantly impacts the mechanical reliability of solder joint interconnects,as widely recognized by the consumer electronics industry. Numerous mechanical behavior studies using a drop test have been reported on ball grid array components with different Pbfree solders. This study is focused on leaded and leadless components in comparison with ball grid array components assembled with Pb-free solder on medium complexity boards. This study is part of a large scale NASA DoD project and
utilized the same board design,assembly,and rework processes of that larger project. Components were attached to the boards using Pb-free solder SAC305. The TSOP-50,TQFP-144,QFN-20,and CLCC-20 components were then hand reworked using conventional SnPb solder to address the sustainment issue. Both 1x and 2x reworks were performed on the non-BGA devices. The PDIP components were also reworked; however,their analysis is not covered in this paper.
In the present work,a board-level drop shock test was performed on nine assemblies,each with 63 components attached. Each board was monitored for shock response and net electrical resistance for all components. In addition,three of these cards were monitored for board surface strain. The assemblies were fixtured to a drop table 3-up and subjected to either 340G or 500G shocks,for a total of 20 drops per board. The shock response,net resistance and strain were recorded in-situ during each drop. The vast majority of the electrical failures occurred on the PBGAs,which were not reworked in this study. Only three of the leaded and leadless components experienced electrical failure.
Damage from the drop shock test was assessed by examining electrically failed and non-failed non-BGA parts by dye-and-pry
and cross-section analyses followed by microstructural examination and defect mapping. It was found that the predominant failure mechanism was board side pad cratering. The cracks propagated through the board material between the laminate and glass fiber under the pad. Electrical failure was only observed when the Cu trace was broken. Of the leaded components that were electrically functional after drop testing,approximately one third were found to be mechanically damaged with pad cratering after dye and pry inspection. This hidden damage may be a reliability concern depending on the field use conditions. Only three leaded components electrically failed,two that were reworked with SnPb solder and one that was not reworked and contained the original SAC 305 solder. Of the two reworked joints that failed electrically,only the TQFP-144,the more compliant leaded component,showed signs of SnPb solder joint fatigue fracture. The failure of the other two components was due to pad cratering and severed traces. There was no correlation found between the number of reworks and the amount of electrical or mechanical failure since only three non-BGA components failed in the test. Most
importantly,this sample set showed no difference in drop test performance between SnPb-reworked and non-reworked Pb-free
solder joints for non-BGA components. More data will be available upon completion of the NASA DoD Pb-free project.

It is frequently noted in surface mount printed circuit board assembly that most solder defects can be traced back to the stencil printing process. In addition,continuous miniaturization trends for electronic components and challenge posed by smaller solder paste deposit requirement,increase focus on stencil printing. Hence,a pristine printer setup,precision tooling,proper squeegee length,stencil type,and stencil aperture design,have become vitally important because of miniaturization trends.
To achieve successful stencil print performance,stencil aperture area ratio and print transfer efficiency are observed to be critical metrics to specify and control. Recent studies suggest that square apertures provide better transfer efficiency than circular apertures,and the argument is raised that given the same area ratio,the volume provided by the square aperture is greater.
This paper is a summary of best practices in optimizing the printing process focusing on comparison of large and small apertures,square vs. round,not with the same area ratio but with similar or the same volume. This paper will definitively clear the air on the round versus square aperture debate.

The solder paste deposition process is viewed by many in the industry as the leading contributor of defects in the Surface Mount Technology (SMT) assembly process. As with all manufacturing processes,solder paste printing is subject to both special and common cause variation. Just like using graduated cylinders from distinctly different manufacturing processes to measure a volume of liquid,using different blades types can contribute significant special cause variation to a process. Understanding the significant differences in print performance between blade types is an important first step to establishing a standard blade for an SMT process.
Over the last 30 years,the SMT assembly process has become increasingly more sophisticated. There are two primary methods of applying solder paste to a circuit board using a stencil printer: squeegee blade printing and enclosed head printing. While each method has its advantages and disadvantages,this study focuses on the squeegee blade printing process and the effects of different types of blades have on the solder paste print deposition quality.
Additionally,solder pastes have been formulated to deliver increased paste deposition volume and consistency for ever decreasing aperture area ratios and increasing print speeds. With squeegee blade printing,only two print parameters can typically be controlled,squeegee speed and downward squeegee pressure. Excessive pressure can result in damaged stencils,coining and breaking of webbing between fine pitch apertures. Too little pressure can result in skips if the stencil is not wiped clean.
This study will report on the effects of squeegee blade thickness along with blade surface finish on solder paste print quality. Print quality is defined here as paste deposit profile,wet bridging and insufficients. Attack angle of the blade,which is considered to be the ultimate factor to be controlled,will be determined using a unique approach as a function of blade thickness,print speed and print pressure. Other aspects of the study will include interaction between the above mentioned factors with various solder paste types. A 3-D Solder Paste Inspection (SPI) system will be used to characterize the print quality in respect to transfer efficiency and deposition profile.

Printing solder paste for very small components like .3mm pitch CSP’s and 01005 Chip Components is a challenge for the printing process when other larger components like RF shields,SMT Connectors,and large chip or resistor components are also present on the PCB. The smaller components require a stencil thickness typically of 3 mils (75u) to keep the Area Ratio greater than .55 for good paste transfer efficiency. The larger components require either more solder paste height or volume,thus a stencil thickness in the range of 4 to 5 mils (100 to 125u).
This paper will explore two stencil solutions to solve this dilemma. The first is a “Two Print Stencil” option where the small component apertures are printed with a thin stencil and the larger components with a thicker stencil with relief pockets for the first print. Successful prints with Keep-Outs as small as 15 mils (400u) will be demonstrated. The second solution is a stencil technology that will provide good paste transfer efficiency for Area Ratio’s below .5. In this case a thicker stencil can be utilized to print all components. Paste transfer results for several different stencil types including Laser-Cut Fine Grain stainless steel,Laser-Cut stainless steel with and w/o PTFE Teflon coating,AMTX E-FAB with and w/o PTFE coating for Area Ratios ranging from .4 up to .69.

An important criterion for dielectric materials used in the microelectronics industry is their flammability. Typically,flame
retardant epoxy resins use bromine-containing flame-retardants. In the electronics industry,non-halogen flame-retardants are
becoming increasing popular due to environmental pressures in the marketplace and in response to recent regulatory issues. However,there is a perception that halogen-free flame retarded systems are more costly and can have performance issues. For example,phosphorus flame-retardants can be expensive and require high dosages,which can have an adverse effect on some properties. For these reasons,new,more cost effective systems with minimum effect of performance properties are desired. Lowering the needed dosage of flame retardant can have lower cost implications and concurrent improvement in properties. Our approach to lowering the required flame retardant dosage was to react low molecular weight of poly (2,6-dimethyl-1,4-phenylene ether),PPE,macromonomer with epoxy resins. The highly aromatic PPE structure exhibits inherent resistance to burning. Indeed,a unique feature of PPE blends and alloys are their ease of flame retarding with phosphorusbased flame-retardants. Therefore,the reaction of PPE macromonomer with epoxy resins offers the intriguing potential of lowering the needed dosage of flame-retardant. For example,the use of 30 and 50-wt% PPE macromer in epoxy resin resulted in a 25-60% reduction in phosphorus-based flame retardant needed for V-0 flame performance. This in turn
improves the odds that physical and mechanical properties of the laminate are not negatively impacted by the flame retardant.
Indeed,the use of PPE macromer in halogen-free FR epoxy resins resulted in a single phase networks with increased toughness,lower dielectric properties,lower moisture absorption,and high glass transition temperatures (Tgs).

The mobile communication devices such as cell phones require high speed transmission of large volume data as well as reduction in size and weight. When signal is transmitted in high speed and frequency on PCB,signal integrity becomes a problem. This problem is getting worse as the transmission becomes faster and larger. Therefore,materials with low Dk/Df are need for high frequency board.
Another requirement for current communication board is environmental friendliness,which is lead and halogen free. As for
laminates,there are some low Dk/Df ones and many halogen free ones. However,material with both is hard to find,quite expensive and difficult to process. Therefore,communication industry is looking for new materials. To meet this demand,a novel halogen free material with low Dk/Df,DS-7402D,has been developed. A hydrophobic epoxy resin was used as base resin to improve the dielectric properties. In addition,a phosphorus containing resin was applied as a hardener and halogen free flame retardant. The resulting material has better dielectric properties,Dk of 3.9 and Df of 0.01,than those of conventional FR-4. It also shows an excellent thermal stability,Td higher than 380C,which makes it suitable for lead-free process. The other properties of this material,such as copper adhesion,modulus and water absorption will be presented.

The electronics industry continues to strive to provide more environmentally friendly products. This movement is partly due to legislation from various countries,partly due to public outcry from well publicized 3rd world recycling practices,and partly due to non-government organizations (NGOs) testing and publishing information on electronic devices regarding their content of various toxic materials. One set of materials targeted for reduction and eventual elimination are halogenated compounds. Halogens are found in plastics for cables and housings,board laminate materials,components,and soldering fluxes. Replacing these halogenated compounds can have a dramatic affect on the PCB assembly process. In this paper those challenges will be discussed as well as techniques and practices that will help ensure high end of line yields and continued reliability.

One of the solder joint failures encountered frequently during Printed Circuit Board Assembly (PCBA) is due to Head-in-Pillow (HiP) defects. The primary cause of HiP defect is due to the warpage of the component during the reflow process. The ultimate solution for solving HiP is to eliminate component warpage however that is very difficult to accomplish in all packages due to various material and construction constraints. Hence,there is a need to find other approaches to solve this problem. One effective solution would be to investigate a solder paste that can mitigate HiP defects.
The theory investigated here presumes that had the BGA spheres maintain contact with the main card solder paste the HiP defect would not occur. Therefore it is during SMT reflow that package warpage raises the BGA sphere(s) up off the applied solder during flux activation and reflow. The BGA sphere only returns to contact the melted/coalesces solder paste during cooling when the package has begun to return to its initial flatness. At this point either the flux is exhausted and is unable to form the joint or the flux itself has created barrier between the two solder features,BGA sphere and PCB solder bump created from the reflow paste on pad.
The Head-in-Pillow defects parts per million (DPPM) level would require a DOE sample size in the thousands therefore this study devised a method to create Head-in-Pillow defect in a controlled lab environment. This method eliminates the use of expensive problematic BGA components and instead applies control over reflow conditions and timing of the contact between the solder ball and the melted solder paste. The SRT BGA rework machine was used to effect programmable control of the time and temperature profile and sphere contact timing.
A baseline SRT process was established using a solder paste common to multiply production line exhibiting HiP defects. The baseline profile was modified until the baseline solder paste consistently created HiP defects. Using these same programmed SRT parameters eight other no-clean solder pastes from different vendors were evaluated. A high resolution video camera was used to record the entire reflow process and track the occurrence of the HiP joint. The performances of all the pastes were analyzed to determine the best solder paste to mitigate HiP defects. The results of this study were incorporated into production and were further validated through the elimination of the HiP joint defect. This test method provides engineers a means to evaluate a solder paste effectiveness in mitigating HiP defects.