High temperature operating life (HTOL) testing was performed on embedded planar capacitors (with epoxy- BaTiO3 composite dielectric) by subjecting these devices to highly accelerated temperature and voltage aging conditions. The objective of HTOL testing was to precipitate avalanche breakdown failures as a result of defects in the composite dielectric. These defects include porosity,voids,and agglomeration of BaTiO3 in the epoxy matrix and are introduced during the manufacturing process. Since these tests were conducted under highly accelerated conditions,the failure mechanisms observed may not occur under the normal operating conditions of this device. However,the results of HTOL can be used in qualification of embedded planar capacitors and to further improve manufacturing processes to reduce the number of these defects.
During HTOL testing,the failure modes observed were a gradual decrease in the capacitance and a sharp decrease in the value of insulation resistance. The sharp decrease in the value of insulation resistance after some time was expected to be governed by the avalanche breakdown (ABD) of the dielectric. The ABD failures were modeled using the Prokopowicz model. The effect of the area of the capacitor and dielectric thickness on the time-to-failure as a result of ABD was also investigated.
A novel failure analysis technique was developed that can be used to locate the failure site of avalanche breakdown and understand the failure mechanism in this material. This technique can also be applied to some other dielectric materials as well. It was also observed that before ABD failures the dielectric material started to show signs of degradation. These degradations were detectable using AC measurements (measurement of dissipation factor) but were not observed in DC measurements (measurement of insulation resistance).

Some ball grid array suppliers are migrating their sphere alloys from SAC305 (3% Ag) or SAC405 (4% Ag) to alloys with lower silver contents and often with “micro alloying” additions. There are numerous perceived reliability benefits to this change,but process compatibility and thermal fatigue reliability have yet to be fully demonstrated. The current study has been undertaken to characterize the influence of alloy type and reflow parameters on low-silver SAC spheres assembled with backward and forward compatible pastes and reflow profiles. This study combines low-silver sphere materials with eutectic tin-lead and lead-free SAC305 solder pastes.
This is the seventh report in a series being published as data become available,and presents the results of the thermal cycling of mixed metallurgy solder joints. Thermal cycling conditions include both 0 to 100oC and -40 to 125oC,with 10 minute dwell times. The accelerated thermal fatigue reliability of mixed Sn-Pb/Pb-free solder joints with varying Ag and “micro alloying” element concentrations are compared to those of 100% Sn-Pb and 100% Pb-free joints for four different package types. Further,the impact of thermal cycle conditions on the rank order of the reliability for the different solder joint compositions is presented. The implications of the data regarding the efficacy of using BGAs balled with low Ag alloys and soldered with Sn-Pb paste,and areas for future work are discussed.

Many BGA and CSP component suppliers have begun shipment of components with a variety of second generation lead-free
solder ball alloys based on the improved mechanical shock resistance. Although in general mechanical performance has been
improved,there have been questions raised on how much the mechanical performance of these lead-free solder ball alloys
can vary with different board surface finishes such as NiAu and OSP.
Mechanical testing was performed on Sn3.5Ag and Sn1Ag0.5Cu 676 PBGA components with 1mm pitch and electrolytic
Ni/Au finished component pads. These components were soldered with Sn3Ag0.5Cu paste on either electrolytic Ni/Au or
high temperature rated OSP board surface finish. The mechanical shock data indicated that among the four board surface
finish/BGA component sphere alloy combinations,the Sn1Ag0.5Cu (SAC105) BGA sphere with NiAu board surface finish
had the lowest drop test resistance among the combinations evaluated,which was not expected.
Failure analysis of this and the other drop test combinations was carried out by dye-pry analysis and cross-sectioning to
understand the failure locations on the soldered BGA joints. The results were assessed in terms of Weibull failure distributions,failure modes,failure locations,and microstructural analysis which included IMC thickness measurement and IMC compositional analysis and distribution. This analysis suggested a possible direct or indirect relationship between drop test results and unique IMC spalling of the Sn1Ag0.5Cu (SAC105) BGA sphere with NiAu board finish. The implications of these findings and areas for further study are discussed.

With a melting point of 199°C,about 20°C lower than the liquidus temperature of SAC305 the Sn-Zn eutectic (Sn~9% Zn) appears to be an attractive candidate as a Pb-free solder. With,at July 2010 market prices,a raw material cost less than half that of SAC305 the Sn-Zn eutectic also has the attraction of substantial cost savings. And,in contrast with Ag,Zn is a relatively abundant element of low toxicity with a comparatively low impact on the environment. The mechanical properties of Sn-Zn alloys are more than adequate in most situations and they have found widespread application in specialised areas such as the joining of high voltage aluminium cables. The Sn-Zn eutectic has,however,found only limited application as a Pb-free solder in electronic assemblies because of early mechanical failure on Cu substrates where the substantial difference in electronegative potential drives galvanic corrosion in the presence of even quite low levels of moisture and ionic contaminants. In this paper the authors report studies that indicate that with the use of a microalloying addition of Mn joint integrity can be maintained on some of the substrates commonly encountered in electronics assembly. Sn-Zn alloy solder joints were exposed to high temperature (150°C) and humid heat (85°C/85% RH) for up to 1000 hours,the mechanical properties measured and the microstructure monitored. Joints were also exposed to salt water and to electric current under conditions of heat and humidity. These studies indicate that there is potential for wider use of alloys based around the Sn-Zn eutectic as solders in electrical and electronic applications.

Properties of printed circuit board laminates are a function of the type and levels of its components. Endeavors to a balance various performance criteria involve balancing the types and amounts of materials that can have similar or opposite effects on key properties. This paper explores the combined use of silica with use of silica and PPE macromonomer in optimizing properties of epoxy-based laminates. Silica exhibits low dielectric properties. However,particulate fillers can lower the toughness of composites. PPE macromonomer has been shown to be very effective in enhancing properties of epoxy resins. In particular,PPE macromer increased the toughness and improved the dielectric properties of epoxy-based laminates. Hence,the combination of PPE macromer and silica filler suggests a way to expand the performance window of epoxy-based laminates. Structure property evaluations were used to quantify the effects epoxy/silica,epoxy/PPE,and epoxy/PPE/silica on dielectric properties,CTE,toughness,and flexural properties. Types of silicas evaluated included ground,fused,platy,and diatomaceous earth. The results showed that using the macromoners in conjunction with silica give performance enhancements over epoxy-silica,or epoxy-PPE alone. Epoxy-based laminates were made which exhibited low Z-axis CTE and low loss tangent.

With ever increasing data transfer rates,insertion loss has become a limiting factor on today's systems.
Insertion loss can be separated into dielectric loss and copper loss. While dielectric loss can be influenced by choosing a base material with the appropriate dissipation factor,copper loss is more complex.
Copper loss is a function of bulk resistivity,cross sectional area of the conductor,conductor surface roughness as well as frequency. Conductor surface roughness is influenced by the copper foil type (STD,LP,VLP,…) and the oxide replacement process during PCB manufacturing.
To better understand the contributing factors to copper loss,the influence of the copper foil roughness,'as received' and 'modified by the oxide replacement? was evaluated.
A DOE was performed with three different types of copper foils (RTF,VLP,ultra low profile) and ten different oxide replacement chemistries. Insertion loss as well as impedance and DC line resistance were measured on the various test samples. The results were compared using a statistical ANOVA approach.
The paper describes the performed measurements and will discuss in detail the influence of copper foil,oxide replacement,line width and copper thickness on the key parameters impedance,DC line resistance and insertion loss. An 'analysis of variances process' is used to understand the level to which the contributing factors affect the electrical parameters.
A measurement at two different frequencies is used to demonstrate the varying influence of the independent variables on insertion loss.

In high frequency circuit boards PTFE is widely used as a substrate material. It offers very low dielectric constant and low losses. However,it is relatively expensive to fabricate,making the cost of PTFE laminates high. In addition PTFE-based circuit boards are composite materials with glass fiber reinforcement and thus not isotropic. Glass fiber also increases losses compared to raw PTFE.
We have developed a new proprietary thermoplastic substrate especially for high frequency circuit boards. This polyphenylene ether (PPE) based substrate offers a low dielectric constant (dk),2.55,and low dielectric loss (df),0.002,in 1 to 5.5 GHz frequency range. It is unfilled,which makes the properties both isotropic and completely homogeneous throughout the substrate. This new material can be processed by typical thermoplastics processing methods,such as film and sheet extrusion and injection molding. Among thermoplastics,PPE is inherently low burning material and it can be easily made flame retardant (V0). However,the addition of flame retardant was found to slightly increase the dielectric loss at high frequencies. This plastic material exhibits a high glass transition temperature,Tg,around 200ºC. This also gives the highest short term use temperature. There is no crosslinked structure to support the substrate above Tg. Processes requiring higher temperatures,such as conventional lead free reflow soldering or wave soldering can not be used.
Because of the very good dielectric properties the material is intended for high frequency applications where the number of required solder connections is limited. One of these is a broadband base station antenna. The performance of this new material as a UMTS/WCDMA antenna for 1.92 – 2.17 GHz frequency band was evaluated with very promising results. First,a patch antenna was designed based on simulations and then the demo antenna was built. The measured performance coincided well with the simulation data. Design of a full size base station array antenna demonstrator is also presented.

In high mix (250+ Assemblies) environments,ensuring small batches are delivered in a timely yet flexible manner without large levels of safety stock and WIP requires the very best of LEAN Manufacturing practices. Dynamic Process Control's (DPC) Material Reservation Manager (MRM) has been designed to provide the tools for major reductions in floor stock and the ability to manage production schedules to maximise utilisation and productivity in this highly dynamic environment.
In line with the current need to dissect volumes into small (<100 unit) Kanban driven batches,using these tools can minimise losses from unplanned changeovers due to missing or un-locatable material.
Any combination of Kanban and ERP/MRP driven order batches can be dynamically loaded automatically in real time. In this example the operators on each of 5 SMT lines perform 'what if's' on each batch. Tracking material reels,matrix trays and sticks loaded on SMT equipment or stored in line locations outside materials controlled storage,we can then check there is sufficient material available to complete the order. If insufficient material is available on the line but is available in material's storage,it is reserved,picked and transferred to the line in time for the orders scheduled start. Shortages preventing production are flagged and the order rescheduled.
Using these tools can reduce waste and eliminate lost time waiting for parts that have been depleted or changing over due to those parts not being available. Every item of material outside of material stores is tracked as it is being used allowing for the application of material FIFO,the use of part used material before new and the real time enforcement of rules such as 'use by dates' and quarantines.

As the assembly of electronic products becomes more automated the collection,storage and retrieval of electronic data demands additional software tools to manage data. The wide spread use of web and email in the delivery of electronic data requires close integration of these data sources to an organization’s data system. A number of new and sophisticated functions are now available within current office software and operating systems but many of these features have gone unnoticed by many users. The purpose of this paper is to identify some of these functions and explain how they can be used to help manage engineering data.

Interest in the adhesive strength of PCBs has recently come to the forefront of the industry. This has been driven by the advent of lead free soldering processes which severely stress the mechanical properties of the board. For sometime,the accepted test method for measuring adhesion in the PCB industry has been the widely used peel strength test. At the same time,it has been common knowledge within the industry that this technique has been less than adequate in guarding against delamination failures during reflow and wave soldering. In recognition of this deficiency,a new test was recently introduced and the test method is now a part of IPC 650; the so called “T260 Method” in which a thermal event is imposed that causes a delamination of the test specimen. The purpose here is to compare the stress field associated with a board delamination to that generated by the peel test and the T260 test.
This analysis will initially give attention to a first principals characterization of the stress field associated with a uniform,free expansion of a PCB,such as in the reflow process. If severe enough,this will result in a delamination. The stress fields produced by the Peel and T260 tests are then analyzed and compared to that of a free expansion. As suspected,the stress fields of the two test methods are significantly different. The stress field created by the T260 test has the same geometry as the free expansion,but a scale factor is required for a total correlation.
Finally a novel technique is suggested for characterizing the layer-to-layer structural integrity of a PCB does not suffer these drawbacks.