According to Prismark Partners,the use of QFNs is growing faster than any package type except for flip-chip CSPs. Prismark
projects that by 2013,32.6 billion QFNs will be assembled worldwide,which represents 15% of all IC packages.
However,QFNs can be a challenge to assemble,especially when it comes to voiding. In most QFN assembly processes,
solder paste is used as a means of attachment. This approach can be problematic,as excessive voiding often occurs due to the
lack of standoff on the component and the high flux content of the paste. The addition of a solder preform can reduce such
voiding by increasing the solder volume of the joint without adding flux volume.
Adding preforms to an assembly process is very easy. Preforms are packaged in tape & reel for easy placement by standard
pick and place machines,right next to your components. The focus of this paper will quantify the preform requirements and
process adjustments needed to use preforms in a standard SMT process. In addition,experimental data showing void
reduction using preforms will also be presented.

The paper discusses on the problems faced by the Assembly,Test Manufacturing (ATM) plants of Intel Corporation for a certain Tape and Reel Process. The problem is generic across the other sister factories around the world. The complexity and high occurrence of the problem result in high customer returns and complaints. The problem was looked at by using Lean and TRIZ. We came up with a potential solution that was both elegant and at the same time would potentially solve the menacing issue at the same time the solution proposed surprisingly yields good returns.

In PCB industry,Optical Inspection has been grown rapidly in past decades. It is now playing an important role in manufacturing process. Most manufacturers are now using AOI machines to report defects on boards after photo-printing or etching. On the other hand,AVI (Automated Vision Inspection) which sometimes also called FVI (final vision inspection) is growing in a relatively fast pace,but not yet widely used in the industry.
AOI and AVI machines are different kind of machines with different functions,but their working principles are very similar. Many technologies of AVI are built up from AOI. This paper analyses on the combination factors of AOI and AVI to meet the inspection objective.
There are 3 parts in this paper. The first part focuses on the application of AOI and AVI and identifies all kinds of defects and boards which they can inspect. The second part compares the hardware and software of AOI and AVI machines. The commons and differences are found out. The third part studies of finding defects under the application and machine issues of AOI and AVI.
The PCB manufacturers are now using AOI and AVI machines to ensure the quality of their boards. Both machines are using cameras to visually find the defects.
What are the differences?
So,we will look into this with the following chapters:
1 – The operation factors of AOI and AVI.
2 – Features of their hardware and software.
3 – How the defects are found
Part 1 – The operation factors of AOI and AVI.

As a result of heightened requirements for quality,integrity and reliability of electronic products,the role of wafer auditing
and nondestructive testing of printed circuit boards and electronic assemblies has grown at an unprecedented rate.
Nondestructive testing improves a product’s performance,increases quality and reliability,and lowers return rate. It is
estimated that the cost of a failure decreases by a factor of ten when the error is identified in the course of production instead
of in the field. Optical and x-ray cameras have become the most efficient and reliable tools for nondestructive testing.
Time delay integration (TDI) method of imaging is based on the concept of accumulation of multiple exposures of the same
object. The primary advantage of this method compared to the conventional line-scan method is the possibility of detecting
low exposure levels with a superior signal-to-noise ratio when high spatial resolution is required.
In the semiconductor industry,TDI-based instruments are used for wafer and reticle inspections where ultraviolet (UV) and
deep ultraviolet (DUV) instruments are mandated by defect detection requirements. In the electronics industry,TDI-based
instruments can be efficiently used for high-speed automated optical inspection (AOI) of high-density electronic assemblies
where dimensions of components populated on the PCB (printed circuit board) become smaller,and spacing between the
components becomes narrower.
X-ray TDI cameras are a critical part of the automated x-ray inspection (AXI) systems used for inspection of multilayer
printed circuit boards and circuit card assemblies with BGA (ball grid array) and other SMT (surface-mount technology)
components. High-resolution x-ray TDI cameras allow efficient inspection of the printed pattern,wire bonding,quality of
soldering of BGA components,and other elements of a PCB structure and circuit assembly.

Signal integrity analysis has shown that printed circuit board (PCB) insertion loss is a key factor affecting high
speed channel performance. Determining and controlling PCB insertion loss have thus become critical production
requirements for achieving multi-gigabit per second data rates. The traditional laboratory method of measuring PCB
insertion loss is difficult to adopt in high volume manufacturing (HVM) environments because it requires expensive
equipment while providing very slow throughput times. In this study we assessed the feasibility of implementing a
simpler and lower cost process to measure insertion loss. Through the use of a new metrology developed by Intel
engineers,we demonstrated it is capable of quickly and accurately measuring PCB insertion loss and is suitable for
use in an HVM environment. Applying this method to a first time study of insertion loss variation in HVM,we
measured lot to lot loss variation to be ~±0.05 Decibels (dB)/inch at 4GHz.

Trace impedances are specified and controlled on PCBs as their nominal impedance value and variations are key factors in establishing
system I/O bus performance. PCB trace impedances are evaluated and controlled during manufacturing using impedance coupon
structures. An issue critical to many high performance I/O busses is that the actual bus impedance is shifted and the intra-bus variation
is larger than measured using the impedance coupons,leading to PCB motherboards being Out of Specification. Recent work has
shown that shifts in measured impedances across a PCB layer is correlated to localized changes in copper density within the PCB
fabrication panel due to both the motherboard design and the PCB manufacture’s selection of fill pattern and impedance coupon
location. Managing the copper density across the fabrication panel through proper coupon design,placement,and copper fill pattern
selection is required to minimize impedance shifts between coupons and product. This paper highlights the impact of copper density on
PCB trace impedances and provides a BKM (Best Known Method) for managing copper density and designing impedance coupons to
minimize impedance shifts and variations that otherwise could lead to Out of Specification impedances on PCB motherboards.

The SMT print process is now very mature and well understood. However as consumers continually push for new electronic
products,with increased functionality and smaller form factor,the boundaries of the whole assembly process are continually
being challenged.
Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest
pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place
components for high density products? …And then on top of this,how can we satisfy some of the cost pressures through the
whole supply chain and improve yield in the production process!
Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil
aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For
next generation components and assembly processes these established rules need to be broken!
New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been
shown to push area ratio limits to new boundaries,permitting printing for next generation 0.3CSP technology. Results also
indicate there are potential yield benefits for today’s leading edge components as well.
Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide
higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print
process.
Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield
processing will be presented.

Many articles have been published indicating that 60 to 75% of all board assembly problems stem from solder paste printing. The important outcome from the printing process is to get the correct amount of solder deposited in the right place. A significant part of that solution is the stencil and its correctness depends on how well its manufacturing process is controlled using proper machines,materials,methods and manpower.
The quality of the stencil can be measured a number of ways: smoothness of the cut wall,material quality,thickness and thickness uniformity of the material,proper aperture location,proper aperture size. This report will show that significant variability exists in aperture size precision between various stencil manufacturing sources.

Many of the latest SMT assemblies for hand held devices like cell phones present a challenge to process and manufacturing engineers with the introduction of miniature components such as .3 mm CSP and uBGA devices as well as 0201 and 01005 chip component devices. Printing these miniature devices along with more conventional SMT devices like .5mm QFP’s and 0603 and 0805 passives,in addition to RF shields is a challenge. Whereas a 4mil (100 micron) or 5 mil (125 micron) thick stencil provides good paste transfer for the normal SMT devices,stencils with this thickness have very low Area Ratios for the miniature devices. For example a .3mm CSP with a 7.5 mil (190 micron) has a .47 Area Ratio for a 4 mil thick stencil.
This paper will examine stencil technologies (including Laser and Electroform),Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings),and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.

The reliability,as tested by thermal cycling,of printed wire boards (PWB) are established by three variables; copper quality,material robustness and design. The copper quality was most influential and could be evaluated pretty accurately by microsectioning methods to determine the general quality of the board. Next in the hierarchy of influence came the robustness of material,and the tertiary influence was design. With the advent of Removal of Hazardous Substances (RoHS) causing lead to be removed from solder and the increase in thermal excursions for assembly and rework to 260C,materials tend to be as much a problem as copper quality in the robustness of PWBs. At the new lead free assembly temperatures the materials tend to break down adding to the failure modes caused by lead free assembly. Both the copper quality and material robustness are improving and now PWB designs are beginning to become more influential in the ability to provide a robust board in a lead-free environment. In this paper we will review the general trends in design like the use of non-functional pads,or nickel as part of the surface finish and rank the overall robustness of each.