The demand for product miniaturization,especially in the handheld device area,continues to challenge the board assembly industry. The desire to incorporate more functionality while making the product smaller continues to push board design to its limit. It is not uncommon to find boards with castle like components right next to miniature components. This type of board poses a special challenge to the board assemblers as it requires a wide range of paste volume to satisfy both small and large components. One way to address the printing challenge is to use creative stencil design to meet the solder paste requirement for both large and small components. Examples of stencil design include step stenciling,dual printing,over-size apertures,etc. The stencil printing process,at its most basic level,involves pushing solder paste through a stencil (with various size apertures) by a squeegee blade. As the squeegee blade and the stencil are in constant contact with the paste during the printing process,their surface characteristics play an important role in the printing process. The most important attribute of a stencil is its release characteristic. In other words,how well the paste releases from the aperture. The paste release,in turn,depends on the surface characteristics of the aperture wall and stencil foil. The recent introduction of a new technology,nano coating for both stencil and squeegee blades,has drawn the attention of many researchers. As the name implies,nano-coated stencils and blades are made by conventional method such as laser-cut or electoform then coated with nano-functional material to alter the surface characteristics. This study will evaluate nano-coated stencils for passive component printing,including 01005. Various print experiments will be conducted using different stencil technology,stencil thicknesses,aperture size,aperture orientation,aperture shapes,and selected paste type,with optimal print parameters to understand the effect of chosen factors on the print quality. Print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.

As consumers the expectation of increased functionality within new products is a given. However there comes a time where this tireless demand for product efficiency starts to stretch the design for manufacture (DFM) rules. Fabricating products with decreasing feature size and increasing complexity is not the issue nor is producing products that have larger components; the dilemma is when products require both.
This predicament is now upon the Surface Mount Assembly (SMA) community,the imminent role out of 0.3mm CSP looks to be pushing the feature size below 200 micron but still RF shields and connectors are required - or put another way heterogeneous assembly is looming upon us.
The main issue surrounding the stencil printing process when dealing with heterogeneous assembly is area ratio (the ratio between stencil aperture open area and aperture wall area). When complying to traditional design rules and maintaining area ratios greater than 0.66 then it becomes near impossible to design a print process for a wide mix of fine and large pitch components.
Whilst developments in solder pastes and stencil manufacturing techniques in recent years have allowed skilled operators to push the area ratio rule of thumb to 0.5-0.6 to accommodate 0.4CSP assembly,the next generation of component technology (0.3CSP’s) is one step beyond this capability.
To address this,new techniques have been investigated with the aim of increasing solder paste transfer efficiency in the screen printing process. Of several techniques investigated one has stood out and has been the subject of intense laboratory trials. The results of this investigation have shown that existing area ratio rules can be seriously challenged and broken to permit 0.3mm pitch CSP assembly within a traditional SMT process. Details of these new developments together with substantive paste transfer efficiency data will be presented.

Handheld portable products such as smartphones are trending toward smaller form factors while simultaneously increasing in functionality to keep up with consumer demands. This is achieved in part by decreasing the size of components and increasing the density of the circuitry. These unique product needs drive different Design for Manufacturing (DFM) recommendations than those that are in use for larger products – while for larger products,reworkability is paramount,for handheld portable products,high first pass yields and fitting the required functionality into an appropriate form factor are of greater concern in many cases.
This paper summarizes a new test vehicle designed to emulate a next-generation smartphone product. One of the goals of this project was to study the effect of pad design and component spacing on assembly yield. The test vehicle includes a representative range of component types including 01005 and 0201 discretes,0.3mm pitch CSPs,Package-On-Package,QFNs,and RF shields. For selected components,different pad designs were included on the board,allowing a direct comparison of the various options and recommendations for the optimal pad designs. In addition,a range of component to component spacings were used on the board,ranging from spacings in common use in today?s products to extremely aggressive spacings that push the limits of the PCB manufacturers. The test vehicles were inspected after assembly,and yields were determined for the various component to component spacings studied to determine what the limitations are and to update DFM rules specific to the needs of extremely dense handheld portable products.
The results of the yield study will be presented along with the analysis of the implications for the DFM rules.

Although many of the QFN and bottom termination products are small in outline and utilize a plastic encapsulated copper
lead-frame structure they do not resemble the more traditional small outline (SOIC) lead-frame packaged semiconductors
because the termination features do not extend beyond the package edge. Many of the QFN packages have an exposed die
attach pad (DAP) feature on the package bottom surface to provide a more direct thermal interface with the mating circuit board surface. Since there is no protruding lead on the package and DAP features are relatively large,solder defects are often beyond acceptable levels.
Key issue: Because the DAP feature can be rather large,printing solder paste with a matching outline can result in uneven solder distribution during the assembly process. This uneven solder distribution causes the parts to tilt,often causing solder bridging and/or disconnect of the perimeter located terminal contacts.
Solution: To compensate for this condition and potentially reduce solder defects,unique DAP print pattern variations can be adopted. Optimizing the solder stencil pattern will ensure that the package bottom surface remains parallel with the circuit board surface during the reflow solder attachment process.
In this paper we will review a wide range of plastic encased no-lead package configurations,industry package standards,and terminal design variations as well as defining the criteria for land pattern design and solder paste stencil development and assembly process methodologies detailed in the new IPC-7093 standard,“Design and Assembly Process Implementation for Bottom Termination Components”.

The CAD library is the starting point that affects every process from PCB layout through PCB manufacturing and assembly. There are dozens of things to consider when creating a CAD library that are often overlooked or not even considered that will directly affect the quality of the part placement,via fanout,trace routing,post processing,fabrication and assembly processes. Part 1 of this paper describes every aspect that should be considered when creating chip CAD library parts and the impact that each feature of the CAD library has in the PCB process.

This paper details the results achieved by the High Density Packaging Users Group (HDPUG) Consortium investigating the hole-wall to hole-wall CAF performance of 20 different Pb-free printed wiring board materials in 20 layer constructions. Seven of the materials are investigated with 2 different 20 layer constructions (different glass styles and resin contents) for a total of 27 different builds. The materials are tested both as built and after Pb-free Reflow at 6x 260C. Materials in the test include high Tg,filled FR4 materials,high Tg halogen free FR4 materials,and high speed materials. Data is presented showing the impact of reflow,the impact of glass styles on the materials and some unexpected CAF results as well.

The propensity of printed circuit boards to electrochemical migration has been assessed traditionally by using surface insulation resistance technique with a DC bias on standard comb structures. Different from this,an AC impedance measurement has been used to evaluate the kinetics of electrochemical migration process and provide detailed information about cell parameters such as solution resistance,charge transfer resistance,and double layer charging capacitance during dendritic growth. The solution resistance and charge transfer resistance decreased during the dendritic growth,while the double layer charging capacitance showed an oscillating nature. The dramatic changes of these parameters due to dendritic growth may be used as forerunner signals prior to dendritic growth and developed as a prognosis technique. A physicochemical model was fitted into the experimental results and a simulation was conducted. The simulation results confirmed the experimental data.

Pad cratering refers to the initiation and propagation of fine cracks beneath BGA pads in organic substrates or printed circuit boards. These cracks,which usually initiate under the application of excessive mechanical loads,represent a serious reliability concern for the industry. In typical board level reliability tests,solder joint failures are detected by an increase in electrical resistance of a daisy chain circuit followed by failure analysis. However,board level testing to determine the onset of BGA pad cratering has been problematic because the early stage of this failure mode is not associated with an electrical signature. Based on the mechanism of pad cratering,it is known that the cracks initiate beneath BGA pads and grow under continually increasing stresses until the pad completely separates from the substrate and a pad “crater” is formed. The catastrophic fracture of an interconnect,which causes an electrical “open”,is in fact the final and most catastrophic stage of the failure. At present the higher strain levels based on electrical resistance monitoring are being reported and used in design practices.
In this study,a new monitoring approach based on acoustic emission has been introduced for early detection of pad cratering failure. Two different lead-free daisy chain test vehicles were used with 1.0 mm pitch HSBGA-1096 and 0.8 mm pitch CABGA-160 packages,and four-point bend tests were performed to induce pad cratering. Acoustic emission activity from the test vehicles was monitored along with the electrical resistance of the daisy chain circuit. The bend test results,in conjunction with failure analysis,have shown that acoustic emission monitoring is indeed an effective methodology to detect the onset of the pad cratering. In contrast,the electrical daisy chain failure was detected at significantly higher strain. Using the acoustic emission approach,it has been found that PCB pad cratering failures can initiate at strain levels significantly lower than previously reported. This board level test methodology may now be used to evaluate the propensity of different materials and packages to pad cratering,and also to improve back-end manufacturing processes without using daisy chain test vehicles.

Surface mount area arrays (SMAA) have been in existence for decades and are increasingly becoming more important as printed circuit board (PCB) assemblies become further complex with package miniaturization and density. Although the PCB space savings afforded with SMAA solder joint technology is advantageous and necessary it is also extremely important that the solder joints formed when using SMAA technology are reliable and robust. A recent advancement in SMAA technology is the solder charge grid array (SCGA). During the development of this new SMAA technology much attention was giving to existing SMAA structures such as the ball grid array (BGA) and column grid array (CGA) with the intent of improving on some of the advantages afforded by each of these technologies. A focus was placed on improvements in the areas of processing,inspection and reliability while maintaining the strengths of existing SMAA features such as density,simplicity and cost. As a result,SCGA technology requires no special processing or equipment during PCB assembly and has been designed to be flexible enough to be used as a drop in replacement for existing BGA or CGA components. SCGA also improves on the co-planarity,inspection,compliancy,and reliability challenges of current SMAA solder joint attachment technologies. This paper will focus on two primary areas of the SCGA: the design and research involved in the development of the SCGA,and the reliability testing completed to insure the SCGA meets industry specifications for SMAA technology and to predict the performance of the SCGA through harsh environments.

As Original Design Manufacturers (ODM) adopt the use of finer pitch connectors,with increased pin count on PCB assemblies. It becomes challenging for Electronic Contract Manufacturing Services (EMS) to build with very low or zero defects in the Printed Circuit Board Assembly (PCBA) operations.
In this paper we will share our experiments for improving the SMT process with these connector types: 1. Samtec’s SEARAYTM (AEAM/AEAF Series) connectors with 500 leads which have a unique solder charge design. The leads themselves are on a 50 x 50 mils pitch from row to row. 2. Two Press-fit SFP Cages with different lead lengths,1 with protrusion and 1 with no lead protrusion on an 18 layer fab (2.5mm thickness).
Case1. Samtec’s SEARAYTM (AEAM/AEAF Series) connector
The connector leads have a solder charge (pre-tin),and the minimum stencil thickness requirement is 6 mils. However the assembly supports a mixture of component technology for this product,where many components need the use of a 4 mils stencil thickness. The fab thickness is 40 mils. There are two main SMT process improvements which we did to eliminate defects: 1. Use 6 mils stencil thickness with a Step-Down to support the 4 mils thickness requirement of other components on the assembly,and replaced the use of a Mini-stencil for the connectors to solve operator handling issue that have been causing damage to the solder charge and others; 2. Based on experimental data,we also adjust the profile for optimization of the solder joints of the connector. With new stencil and oven profile,the defects reduced from 15% to < 0.5% for the connector.
Case2. Two Press-fit SFP cages with different lead lengths
Because there were issues with these Press-fit SFP cages failing mechanical drop test. The customer requested us to add solder to the peripheral row of pins of the SFP cages,for a stronger retention to the fab. We couldn’t make all pins have a good solder joint with a Non-modified wave fixture,and wave as a normal process. Therefore,we have new process designs (a. Modified wave fixture,add flux on the top side of PCB,and wave as a normal process for the 2 different vendor’s components; b. A non-modified wave fixture and add flux on the top side of PCB and wave as a normal process; c. Modified wave fixture and wave as normal process). All these Selective Wave process methods are working: these cages now have good retention with the fab,passing mechanical drop test,and no defective pins for current boards were building. We use 2DX with tilting angle detector to check the solder joints of the cages.
We used 2DX machine to identify boards with critical connectors by optimized method.