While most cleaning processes in the global electronics manufacturing industry still rely on cleaning with DI-water only (for OA flux removal),recent studies suggest that water is beginning to reach its cleaning limitation,favoring the use of chemically assisted cleaning processes. The increased use of water-soluble lead-free solder requires more activators and higher soldering temperatures,which result in more burnt-in fluxes and produce water insoluble contamination. DI-water alone has a limited to no ability to solubilize non-ionic residues on the board’s surface.
These findings coincide with the use of smaller,more densely packed components which further limit the effectiveness of pure DI-water. Due to its high surface tension of over 70 dynes/cm,water cannot effectively penetrate underneath low standoff components. Chemistry assisted cleaning processes,however,can reduce the surface tension to 30 dynes/cm and below and therefore eliminate penetration problems.
This technical case study complements the authors’ initial in-house findings by comparing them to actual production assemblies and conditions. The lead engineering team at a participating customer site designed this comprehensive blind study to determine removability with DI-water versus various chemistry supported systems. The findings revealed significant experimental data,which shed much needed light on this emerging industry challenge.

Cleaning flux residues post soldering has been a high reliability criterion practiced by assemblers of military,aerospace,automotive,medical devices and other value offerings. Highly dense advanced packages reduce spacing between I/Os and
standoff heights. The complexity of removing flux residue increases,while elevating the risk of white residue under low
standoff (gap) components. To address this concern,many electronic assemblers use water soluble solder paste and clean
post soldering. The purpose of this factorial designed experiment is to evaluate multiple water soluble flux materials and cleaning chemistries,including DI water only,to determine the best chemical properties for removing lead-free water soluble flux residues. The optimal process parameters will be defined with data findings analyzed and presented using statistical analysis and models.

The present work describes the use of additives in formaldehyde-free copper solutions to improve the start reaction of
electroless copper deposition.
Conventional electroless copper plating solutions contain a copper salt,one or several complexing agents,a reducing agent,a pH adjusting agent as well as stabilizers and other additives.
At the present time formaldehyde is the established reducing agent in electroless copper metallization of plated throughholes.
Because of its environmental impact,there is a need to replace formaldehyde. Many alternatives have been suggested but some of them pose a greater health and safety threat than formaldehyde does and some alternatives are not economically viable.
In this investigation,the more environmentally friendly glyoxylic acid is used as an autocatalytic reducing agent. However glyoxylic acid is more expensive and causes undesirable side reactions. Consequently,it leads to a rise in the price of the copper plating process. In order to keep process costs under control,the concentration of glyoxylic acid in the copper bath should be reduced without affecting the quality of the copper deposits.
Therefore,additives are introduced which can compensate for the lower reducing agent concentration,and thus the lack of essential electrons for the copper deposition. On palladium-activated base material,the additives react with the palladium and generate additional electrons in the initial phase of the deposition. Thus,the adequate supply of electrons from two sources permits the deposition of a homogeneous and compact copper layer.

Typical electrodeposition of conventional metals produces deposits that are polycrystalline in nature,comprised of many crystal grains separated by grain boundaries. Adding grain refiners to a plating solution and employing pulseplating techniques can reduce the grain size and produce a nanocrystalline deposit. The average grain size of the nanocrystalline copper deposit is about 100 nanometers. This is about 80 times smaller than the conventional deposit
average grain size of 2 microns. Nanocrystalline copper deposits have negligible porosity and superior physical,mechanical,and electrical properties. The hardness,strength and wear resistance of the deposit are greatly enhanced. Stress corrosion cracking is virtually eliminated,while the hydrogen diffusivity and solubility are increased. This paper compares the electrochemical,mechanical,and physical properties of nanocrystalline copper deposits with
conventional polycrystalline copper deposits on printed wiring boards (PWB). Test boards were evaluated after thermal shock and thermal stress tests. Copper thickness and uniformity are evaluated both by microsection and Xray fluorescence measurement techniques.

The use of an Organic Metal finish only a few nano-meters deposited onto copper pads of printed circuit boards provides effective protection against oxidation and preserves solderability. The Nano layer has a thickness of only 50 nm,and contains the Organic Metal (conductive polymer) and a small amount of silver. Being more then 90% (by volume),Organic Metal is the major component of the deposited layer; Ag is present equivalent to a thickness of 4 nm. This Organic Metal – Ag complex final finish performs as well as any of the established surface finishes with a significant reduction in energy and environmental impact.

For many of the Pb-free solders required under the European RoHS directive,there is now sufficient information,primarily in the form of the results of accelerated thermal cycling of various levels of severity,to develop acceleration models for the creep-fatigue of these solders. In this paper the parameters for the SAC405/305,SAC205,SAC105 and SnAg to replace the parameters for eutectic SnPb in the well-established Engelmaier-Wild solder creep-fatigue model.

This presentation discusses critical material properties and test data that are often overlooked in the introduction of new lead-free solder alloys,but are critical to alloy comparison and the development of life predictive models and acceleration factors. Common gaps in property and test database are identified (e.g.,lack of creep data at low to medium stress and cold temperature,insufficient data under mildly accelerated test conditions). The importance of variations in temperature variables (cold and hot
temperatures) as well as dwell times is also discussed. Examples of thorough test conditions and test databases that have been used for the development of SAC305,SAC387/396 acceleration factors are presented. It is concluded that the “winning” alloys - i. e. alloys that end-users can work with – are those that are fully characterized in terms of metallurgy (including at interfaces) and mechanical / physical properties & their evolution; are robust enough under both thermal and mechanical loading conditions; and come with an extensive reliability test database and validated reliability models & acceleration factors.

Predicting the electrical performance of embedded capacitor PCB designs has been a major stumbling block for the technology. In particular,one of the key questions has been how quickly can charge be delivered to a device from the embedded capacitor. As pointed out in earlier papers (1,2) the major attenuator is the via connection between the ground plane and the embedded capacitor. These studies determined the performance when all of the charge is delivered through a single via. The index of performance for these investigations was the time constant associated with the capacitor’s discharge. It was found that a major reduction in inductance and hence the time constant could be achieved by minimizing the barrel length of the via; usually using blind vias.
The core of this paper examines other techniques for reducing the effective time constant and thereby improving performance. A potential strategy is using multiple vias between the device and the embedded capacitance. The analysis consists of developing a mathematical model of the circuit using the “lumped sum” approach commonly used in most electronic circuit analysis. With the model,we are able to predict the performance of the embedded sheet capacitor with multiple vias. Potential avenues for performance enhancement can then be identified.

Mixing PCB Design Layout units will compromise perfection every time. PCB Design perfection starts with building CAD
library parts and quickly moves to part placement,via fanout and trace routing challenges. Outputting data for machine
production can be extremely complex or very simple based on the PCB Design Layout units that were used throughout the
PCB design process. This paper reviews one of the single most important,but sometimes overlooked or taken for granted,
aspects of the electronics industry – The PCB Design Grid System

As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC,at the IC package,at the module,at the hybrid,the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The industry must address the technology gap between printed boards and semiconductor technology and how the semiconductor and IC packaging suppliers can combine resources in furnishing viable solutions. Although the development of fine-line substrates and assembly refinement has narrowed the gap somewhat,minimizing component outline,the array contact
format and reduced contact pitch is proving to be the most practical solution for uncased flip-chip and die-size package
applications.
This paper outlines the basic elements furnished in the newly released IPC-7094 ‘Design and Assembly Process Implementation for Flip-Chip and Die Size Components’ providing a comparison of existing and emerging wafer level and chip-size package methodologies. It will focus on the effect of PCB design and assembly of bare die or die-size components in an uncased or minimally cased format. The PCB design guidelines and assembly process variations furnished will provide useful and practical information to those who are considering the adoption of miniature bare die or die size array components.