3D is the shorthand term for the three dimensions of Cartesian coordinate space X,Y and Z. With that definition in mind,one will find with little or no stretching of the imagination,that the first electrical interconnections,performed using discrete wires were unquestionably 3D. If one doubts it they can look at almost any electrical product from the time of the 19th century telegraph onward. 3D interconnections are found virtually everywhere. It is really 2D that is more illusive if one thinks about it. Even so,3D interconnection solutions and options have dominated the electronics manufacturing industry's attention over the last few years and interest in the topic has been accelerating. The reasons for this interest are manifold but the root cause is that the third dimension provides the ability to extend the pursuit of ever greater density when the acknowledged physics based limits that will ultimately spell the end of Moore's Law kick in. In order to keep delivering the promise of better cost/performance metrics for each new generation of electronics,interconnection technologies which take advantage of the third dimension will play an increasing important role in the future. In fact electronic interconnection
technologies will undoubtedly pace price and performance improvements for most if not all future electronic products and 3D
interconnections will play a pivotal role. This paper discusses 3D solutions which have been used from past to present from chip to system and will included a glimpse of what might be ahead.

After the implementation of RoHS and the discontinued use of lead bearing products and the introduction of lead free (LF)
solders,tin and its alloys have come to the forefront as the first choice of replacement to tin-lead.
On the solder side the transition has moved forward and solutions have been implemented,like the SAC family of LF solders
for paste reflow and tin-copper for HASL (hot air solder leveling). The industry is constantly making progress adapting its
materials and processes to the higher reflow temperature profile for these LF solders. Today there is a much better
understanding of the types of solder joints that are formed; their reliability and the type of intermetallic compound (IMC)
formed.
On the surface finish side,replacing tin-lead has posed greater challenges. Component leads and connector finishes were
being converted to tin as an obvious alternative. This works well as a soldering surface,however any part of the lead or the
connection surface that is not soldered to,has shown a potential to form tin whiskers over the life of the part. Internal stresses
in the deposit due to IMC formation or external stresses on the deposit are known to initiate whisker formation.
In this paper two approaches are implemented to dissipate the stress that is formed,the first is to modify the substrate surface
to control the growth in thickness and direction of propagation of the IMC and the second is to modify the large columnar tin
deposit crystal structure to mimic the fine equiaxed structure of tin-lead solder. The former is achieved thru controlled micro
roughening of the substrate and the latter by the use of additives to the plating bath.
Data will be presented to show the effect of each of the two approaches on the dissipation of the stress,resulting from IMC
formation. As the stress is dissipated the primary cause of whisker formation is eliminated.

In recent years the PCB industry has increasingly turned to digital,or maskless,imaging techniques in order meet demands for tighter registration between layers. Many of these techniques,including laser direct imaging (LDI),rely on a “dot-matrix” style exposure technique that uses “binary” pixels and small pixel or dot spacing to achieve the required resolution. This results in limitations in write speed and throughput,since many small pixels or dots must be written over a relatively large area PCB substrate. A patented gray level technique1 based on a commercially available digital micro-mirror device (DMD) achieves required resolutions with a relatively large projected pixel size,and thus offers a higher speed alternative to conventional digital techniques. Gray level,or dose control as a function of panel position can also provide some degree of compensation for minor processing or development artifacts that are known to recur in the same areas of a panel.

•Background and Objective
•Head-in-Pillow (HiP) Defect
•In Circuit Test (ICT) Testability
•Evaluation Steps
- Solder Paste Selection
- Head-in-Pillow Test
- Printability & Solderability Tests
- Surface Insulation Resistance (SIR),Electrochemical Migration (ECM) & Ion Chromatography (IC) Tests
- Verification Build

•Overview
•Test Method Considerations
•Proposed Test Methodology
•PCB,Stencil & Part Information
•Pick-up Adapter Design
•Test Setup Overview
•Head-in-Pillow Defect Detection
•Test Parameters
•Thermal Profile Comparison
•Test Results Classification
•SnPb & Pb-free Solder Paste Testing Results
•Influence of Flux Dip

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As technology becomes increasingly reliant on electronics,understanding the longevity of lead-free solder also becomes imperative. This research project focused on phase transformation kinetics within SAC 305 lead free solder during thermal aging processes. Today in the electronics industry,it is the most widely used solder,making it a high priority to understand its long-term stability and performance in a variety of service conditions. Reaction kinetics during thermal aging has being studied to parallel a previous research project concerning the activation energy to form Cu3Sn1. Results from the previous project will be included for the purpose of comparison.
The previous research project was designed to determine which application parameters will immediately cause the growth of the detrimental Cu3Sn1 layer. The data was useful in predicting the amount of growth within this layer during soldering. The current research has analyzed the effect of various aging temperatures on the initial growth of Cu3Sn1.

Although many predicted the demise of through-hole components,they are alive and well with tens of billions used each year. In mixed SMT/through-hole PCBs,through-hole components,and especially connectors,are often used for their mechanical robustness. A typical example would be a USB connector in a laptop PC. Typically an SMT connection just doesn’t have the mechanical robustness needed to support multiple connector plug-in and removals. However,performing a full wave soldering process to assemble a few through-hole components on a mostly SMT PCB doesn’t usually make economic sense and may damage the PCB. In such situations,the best option is often to assemble the through-hole components and connectors with a selective soldering process.
This paper touches on identifying favorable flux properties,down-selecting low solids fluxes for lead-free selective wave soldering,the selective soldering process itself,and testing criteria. Topics reviewed will be the flux selection,optimizing the selective soldering process by varying the flux concentration,pre-heat parameters,soldering temperatures,and dwell time. The paper will finish with a summary of the work and a systematic process to select a flux and optimize the selective soldering process for high yields and quality.

The Pin in Paste (PiP) technology is the process of soldering Pin through hole (PTH) components using the Surface Mount Technology (SMT) reflow process. The use of PiP process offers several advantages compared to the traditional wave soldering process. One of the primary advantages is lowering of cost due to the elimination of the wave soldering process and its associated tooling cost and potential handling damage. Another advantage is that with the wave soldering process,it is extremely difficult to achieve adequate holefill on thermally challenging thick Printed Circuit Boards (PCBs). However,by using PiP process with combination of solder preforms,it is possible to achieve adequate holefill and reliable solder joints for soldering PTH components.
The objective of this study is to investigate the use and limitations of machine-placed solid solder preforms during the top-side SMT reflow process for PTH components. An experiment was designed to investigate the following problems:
1) How much additional volume is provided by the combination of printed solder paste plus preforms in determining final barrel fill volume?
2) How far away from the hole can the paste and preform extend and still coalesce during reflow?
3) What is the optimum lead to hole ratio for the use of solder preforms?
4) What is the effect of pin protrusion on the PiP process?
5) What are the limitations in placing preforms within printed solder paste?
6) What are the design considerations required for the different / various PTH components to be suitable for the PiP process with solder preforms?
7) What is the effect of different types of solder masks on the PiP process?
The experiment was conducted on a 130 mil test vehicle using both tin-lead and lead-free materials and processes. The results of this designed experiment along with the inspection methods are presented and discussed in detail in this paper. The outcome of this study will thus provide process engineers extensive guidelines for implementing PiP technology with combination of solder preforms.

Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size,such as a near die size footprint,thin profile,and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size,weight,electrical,and thermal properties are important. However,adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow,outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength,ductility,creep,and fatigue life. In addition,voids could also produce spot overheating,lessening the reliability of the joints. This is particularly a concern for QFN where the primary function of thermal pads is for heat dissipation. Thermal pad voiding control at QFN assembly is a major challenge due to the large coverage area,large number of thermal via,and low standoff. Both design and process were studied for minimizing and controlling the voiding. Eliminating the thermal via by plugging is most effective in reducing the voiding. For unplugged via situations,a full thermal pad is desired for a low number of via. For a large number of via,a divided thermal pad is preferred due to better venting capability. Placement of a thermal via at the perimeter prevents voiding caused by the via. A wider venting channel has a negligible effect on voiding and reduces joint continuity. For a divided thermal pad,the SMD system is more favorable than the NSMD system,with the latter suffering more voiding due to a thinner solder joint and possibly board outgassing. Performance of a divided thermal pad is dictated by venting accessability,not by the shape. Voiding reduction increases with increasing venting accessability,although the introduction of a channel area compromises the continuity of the solder joint. Reduced solder paste volume causes more voiding. Short profiles and long hot profiles are most promising in reducing the voiding. Voiding behavior of a QFN is similar to typical SMT voiding and increases with pad oxidation and further reflow.