- COMPONENTS
- Risk Mitigation Testing Strategies Examples
- Risk Mitigation Testing Affiliations
- IDEA – 1010
- AS5553
- Mil-Std-1580

Counterfeiting is a widespread problem that affects every industry and which has the potential to significantly erode a company’s bottom line. According to the International Anti-Counterfeiting Coalition (IACC),the global trade in counterfeit products has increased from $5.5 billion in 1982 to approximately $600 billion annually today. In the U.S. alone,counterfeit goods cost businesses between $200 billion to $250 billion annually [1].
The impact of counterfeit products is not just about tangible financial losses. Counterfeit products can negatively impact a company’s brand,reputation and perceived commitment to quality. Because counterfeit products can also expose consumers to potential safety hazards,their availability may carry legal ramifications for companies.
The good news is that companies can assess the risk of being targeted by counterfeiters,and can implement a plan to protect against such risks. By following the appropriate steps,companies can determine how to protect their physical and intellectual property assets,identify the elements of an anti-counterfeiting program and implement an anti-counterfeiting plan. However,any anti-counterfeiting plan must be tailored to a specific company’s needs,based on size of the company,the type of products,the complexity of the supply chain and the markets in which the company does business.
Many companies have taken rigorous steps to protect their intellectual property,the quality of their products and their reputation in the marketplace. These steps include the introduction of holographic labels,the use of special color schemes to identify specific product types and the application of overt and covert security coding. In addition,a number of companies have partnered with customs officials in anti-counterfeiting efforts,resulting in the seizure of millions of counterfeit products,including electronic products.

DNA is a form of forensic evidence trusted by law enforcement and recognized by international courts around the world. This abstract provides an introduction to the utility of botanical DNA taggants to safeguard electronic components in supply chains and to protect against counterfeiting and diversion. A detailed treatment of the science behind Applied DNA Science’s botanical DNA technology,its applications to semiconductors and microchips and an overview of DNA analysis by PCR and CE analysis is provided.

Counterfeit electronic parts have become a significant cause of worry in the electronics part supply chain. Most of the counterfeit parts detected in the electronics industry are either new or surplus parts or salvaged scrap parts. The packaging of these parts is altered to modify their identity or to disguise the effects of salvaging. The modification can be as simple as the removal of old marking and then adding new marking,or as complicated as recovery of a die and repackaging.
In this chapter,we discuss the type of parts used to create counterfeits and the defects/degradations inherent in these parts due to the nature of the sources they come from,proposed inspection standards,and limitations of these standards. The processes used to modify the packaging of these parts to create counterfeits are then discussed along with the traces left behind from each of the processes. We then present a systematic methodology for detecting signs of possible part modifications to determine the risk of a part or part lot being counterfeit.

Several U.S. Government (USG) regulations require parties engaged in import activities to maintain records of transaction processes. By using formal documented tools integrating these regulations within existing quality management systems,organizations can mitigate risk throughout their supply chain and simultaneously comply with AS5553.

For the electronics on PCB’s,dielectric materials provide not only material and media support for the high-speed digital and RF systems,but also electrical performance. Impedance control and signal integrity have become increasingly important in high frequency applications,while trends in electronic industry continue to drive high-speed digital,RF and microwave systems for high-density integration,high system performance and high power operations over a wide range of operating temperatures. Microstrip and stripline are widely used in the high data rate and high frequency circuitry designs because they can be easily and cost-effectively fabricated with high performance,planar PCB laminates for various applications. To obtain optimal signal/power transmission,signal integrity and low signal distortion,certain controlled impedance (typically 50O) is very important to minimize impedance mismatching and power reflection. In practical designs,characteristic impedance of transmission lines is a complex function of substrate dielectric properties and physical structures,such as dielectric constant (er),trace width (W) and substrate thickness (h or b),or even metal strip thickness (t). However,when designers come to selecting the proper PCB laminates for their designs,there is lack of design tools for them to quantitatively evaluate the target board materials in terms of impedance control to effectively compare their temperature performance in terms of key PCB material properties,such as dielectric constant thermal stability and substrate thermal expansion. In this paper,based on the practical design equations for microstrip and stripline circuitry and using the Taylor series expansion (e.g. ?Z=dZ/dk*?k+dZ/dW*?W+dZ/dh*?h+dZ/dt*?t) for linear approximation of multiple-variable functions (e.g. Z0=Z(k,W,h,t)),analytic design equations for evaluating the transmission line impedance variations from its board dielectric and dimensional change have been developed. Additionally,these analytic design tools can also be readily applied to evaluate the variations of planar transmission lines for practical design and PCB fabrication impedance control with the board material’s dielectric constant and dimensional stability resulting from substrate tolerances (i.e. laminate DK and thickness tolerance) and PCB processing (such as trace etching resolution,multilayer thickness and etc.).

Over the years a question that has been asked repeatedly of material suppliers is: “when do I need to use a high frequency laminate over the choice of a standard FR-4 substrate”? The answer has many aspects to consider. There are circuit fabrication issues,assembly concerns and end-use performance needs. Of course there are material issues as well and how the material interacts with some of the other stated concerns.
To compound this issue there are many different types of high frequency laminates. Some laminates are nearly pure PTFE,filled PTFE and some are thermoset hydrocarbon systems. Of these different high frequency laminates there are also tradeoffs to consider.
This paper will give some guideline as to understanding when to choose between FR-4 and high frequency materials. The different areas considered will be basic material properties,circuit fabrication,reliability and end-use performance needs. Later in this paper the end-use needs will be expanded to include electrical performance issues,in an effort to address the often asked question about when do you actually need the improved electrical performance of the high frequency laminate over an FR-4 substrate. Lastly a topic that is becoming more prevalent will be discussed and that is multilayer hybrid PCB’s (printed circuit boards) using a combination of FR-4 and high frequency materials.

Test and quality coverage for an assembled printed circuit board is becoming increasingly more expensive and complex as digital electronics moves well into the gigahertz era. Traditional tools like time domain (TD) statistical simulation and Bit Error Rate Testers (BERT) are presently used to verify and test gigabaud digital designs. Unfortunately not only is a very high level of technical experience is required,but just the logistics of the setup can be monumental. The proposal is to use a few simple scalar metrics like signal to noise ratio (SNR) to let the quality of a board stand simply on its own electrical merits. These new metrics are much easier to acquire from scattering parameters than traditional simulation or BERT testing.
They are an outgrowth of the IEEE 10 Gigabit per second backplane standard work.
Context and usage models are presented as discussion of frequency domain (FD) interconnect metrics are developed. One such usage is that electrical board quality can be mapped on a trace by trace basis in terms of an associated scalar electrical quality factor or metric. These metrics may become the basis of an “exchange metric” between customer and vendor.

•iNEMI Environmental Vision
•Highlights of Environmental Conscious Electronics Chapter of iNEMI Roadmap
•Key iNEMI Projects
•Environmental Impact of Electronics
–Products
–Services
•Concluding Thoughts

In today’s PCB industry,the challenges are no longer just on how to control and improve the manufacturing
processes,but also to ensure the fabricated product is compliant to the industry standards and leads to high quality. Due to the
requests for more detailed information about the products,numerous techniques for PCB characterization were developed. In
this paper,we proposed the Enhanced Root Impulse Energy (e–RIE) loss method. The original RIE was presented in the
papers and presentations of IPC meetings. Different from previous work,instead of directly differentiating the time–domain
TDR waveform and using it as the impulse response h?t ?,the e–RIE method implements the time–domain Thru–Reflect–
Line (t–TRL) calibration technique on the time–domain TDR/TDT measurements. The t–TRL is a complete calibration
technique and it removes the discontinuities due to the transition from SMA connectors to the stripline launches and
improves the accuracy of impulse response measurement and the RIE loss calculation. Excellent agreement is achieved for
the RIE losses obtained from the t–TRL and the VNA measurements. Also in the paper,the relationship of the RIE loss and
loss tangent is studied. Based on the theoretical derivation,the RIE loss is calculated as a function of tan? for a given pair of
test and calibration lines. The sensitivity of RIE loss vs. different test and calibration pairs is studied. Overall,the longest test
line (>10 inches) and the shortest calibration line (<1 inch) give the best RIE loss sensitivity. The e–RIE extended the
applications of the original RIE method and it provides a simple and practical test method for the transmission line loss
characterization in high–volume PCB manufacturing.