Several U.S. Government (USG) regulations require parties engaged in import activities to maintain records of transaction processes. By using formal documented tools integrating these regulations within existing quality management systems,organizations can mitigate risk throughout their supply chain and simultaneously comply with AS5553.

For the electronics on PCB’s,dielectric materials provide not only material and media support for the high-speed digital and RF systems,but also electrical performance. Impedance control and signal integrity have become increasingly important in high frequency applications,while trends in electronic industry continue to drive high-speed digital,RF and microwave systems for high-density integration,high system performance and high power operations over a wide range of operating temperatures. Microstrip and stripline are widely used in the high data rate and high frequency circuitry designs because they can be easily and cost-effectively fabricated with high performance,planar PCB laminates for various applications. To obtain optimal signal/power transmission,signal integrity and low signal distortion,certain controlled impedance (typically 50O) is very important to minimize impedance mismatching and power reflection. In practical designs,characteristic impedance of transmission lines is a complex function of substrate dielectric properties and physical structures,such as dielectric constant (er),trace width (W) and substrate thickness (h or b),or even metal strip thickness (t). However,when designers come to selecting the proper PCB laminates for their designs,there is lack of design tools for them to quantitatively evaluate the target board materials in terms of impedance control to effectively compare their temperature performance in terms of key PCB material properties,such as dielectric constant thermal stability and substrate thermal expansion. In this paper,based on the practical design equations for microstrip and stripline circuitry and using the Taylor series expansion (e.g. ?Z=dZ/dk*?k+dZ/dW*?W+dZ/dh*?h+dZ/dt*?t) for linear approximation of multiple-variable functions (e.g. Z0=Z(k,W,h,t)),analytic design equations for evaluating the transmission line impedance variations from its board dielectric and dimensional change have been developed. Additionally,these analytic design tools can also be readily applied to evaluate the variations of planar transmission lines for practical design and PCB fabrication impedance control with the board material’s dielectric constant and dimensional stability resulting from substrate tolerances (i.e. laminate DK and thickness tolerance) and PCB processing (such as trace etching resolution,multilayer thickness and etc.).

Over the years a question that has been asked repeatedly of material suppliers is: “when do I need to use a high frequency laminate over the choice of a standard FR-4 substrate”? The answer has many aspects to consider. There are circuit fabrication issues,assembly concerns and end-use performance needs. Of course there are material issues as well and how the material interacts with some of the other stated concerns.
To compound this issue there are many different types of high frequency laminates. Some laminates are nearly pure PTFE,filled PTFE and some are thermoset hydrocarbon systems. Of these different high frequency laminates there are also tradeoffs to consider.
This paper will give some guideline as to understanding when to choose between FR-4 and high frequency materials. The different areas considered will be basic material properties,circuit fabrication,reliability and end-use performance needs. Later in this paper the end-use needs will be expanded to include electrical performance issues,in an effort to address the often asked question about when do you actually need the improved electrical performance of the high frequency laminate over an FR-4 substrate. Lastly a topic that is becoming more prevalent will be discussed and that is multilayer hybrid PCB’s (printed circuit boards) using a combination of FR-4 and high frequency materials.

Test and quality coverage for an assembled printed circuit board is becoming increasingly more expensive and complex as digital electronics moves well into the gigahertz era. Traditional tools like time domain (TD) statistical simulation and Bit Error Rate Testers (BERT) are presently used to verify and test gigabaud digital designs. Unfortunately not only is a very high level of technical experience is required,but just the logistics of the setup can be monumental. The proposal is to use a few simple scalar metrics like signal to noise ratio (SNR) to let the quality of a board stand simply on its own electrical merits. These new metrics are much easier to acquire from scattering parameters than traditional simulation or BERT testing.
They are an outgrowth of the IEEE 10 Gigabit per second backplane standard work.
Context and usage models are presented as discussion of frequency domain (FD) interconnect metrics are developed. One such usage is that electrical board quality can be mapped on a trace by trace basis in terms of an associated scalar electrical quality factor or metric. These metrics may become the basis of an “exchange metric” between customer and vendor.

•iNEMI Environmental Vision
•Highlights of Environmental Conscious Electronics Chapter of iNEMI Roadmap
•Key iNEMI Projects
•Environmental Impact of Electronics
–Products
–Services
•Concluding Thoughts

In today’s PCB industry,the challenges are no longer just on how to control and improve the manufacturing
processes,but also to ensure the fabricated product is compliant to the industry standards and leads to high quality. Due to the
requests for more detailed information about the products,numerous techniques for PCB characterization were developed. In
this paper,we proposed the Enhanced Root Impulse Energy (e–RIE) loss method. The original RIE was presented in the
papers and presentations of IPC meetings. Different from previous work,instead of directly differentiating the time–domain
TDR waveform and using it as the impulse response h?t ?,the e–RIE method implements the time–domain Thru–Reflect–
Line (t–TRL) calibration technique on the time–domain TDR/TDT measurements. The t–TRL is a complete calibration
technique and it removes the discontinuities due to the transition from SMA connectors to the stripline launches and
improves the accuracy of impulse response measurement and the RIE loss calculation. Excellent agreement is achieved for
the RIE losses obtained from the t–TRL and the VNA measurements. Also in the paper,the relationship of the RIE loss and
loss tangent is studied. Based on the theoretical derivation,the RIE loss is calculated as a function of tan? for a given pair of
test and calibration lines. The sensitivity of RIE loss vs. different test and calibration pairs is studied. Overall,the longest test
line (>10 inches) and the shortest calibration line (<1 inch) give the best RIE loss sensitivity. The e–RIE extended the
applications of the original RIE method and it provides a simple and practical test method for the transmission line loss
characterization in high–volume PCB manufacturing.

Circuit housings used in industrial and utility applications have requirements often not needed in the commercial or consumer electronics industries. The device may be used in locations as diverse as in a chemical factory,wind turbine,transit station,offshore platform,wastewater control panel,or a Smart Grid communications box. These applications often require a high degree of resistance to shock and vibration. They may also be required to operate over wide temperature ranges,especially if mounted in outdoor locations where a lot of electronic equipment is now deployed. They might need to adhere to specific shielding requirements or conform to certain physical sizes and shapes. Others may require DIN mounting options or have touch-safe connector requirements. This presentation will introduce the audience to these issues and provide information about how organizations such as the IEC address them with standards and approvals.

It is widely known and understood that the overall cost and quality of a product is most influenced by decisions made early in the design stage. Finding and correcting design flaws later in the product development cycle is extremely costly. The worst case situation is discovering design problems after failures occur in the field.
Designing for reliability has been “easier said than done” due in large part to the many competing interests involved in a design. For example,the designer is challenged with increasing the product performance while continually reducing the form factor. The reliability engineer may raise concerns about design risks,but without the ability to quantify the potential impact,they are often unable to meaningfully influence the design decisions. Implementing a newly developed reliability prediction analysis tool,Sherlock,will forever change this equation. Before a single product is built,this valuable new tool enables the engineer to import the design files and quantitatively predict the life of the product according to the assumptions made for the user environment. The failure rate is predicted for thermal cycle fatigue of solder joints and plated through hole vias as well as for shorting from conductive anodic filament (CAF) formation. The software also produces a finite element analysis of the circuit boards showing regions susceptible to excessive board strain during vibration or shock events. The greatest value comes from the ability of the engineers to perform various “what if” scenarios to determine the impact of any number of design choices.
? What if I change the mount point locations?
? What if I change the via diameters,the spacing,or the copper thickness?
? What if I change the laminate thickness or material selected?
? What component is at highest risk of failure and what if I change its? format?
? What is the reliability impact of changing from SnPb to SAC305 solder?
Finally,once the design has been optimized to satisfy the many competing requirements,the software can be used to predict the rate of failure over the lifetime of the product. This information can then be used to more accurately plan for the warranty costs. With margins shrinking in the electronics industry,OEMs depend more on profits from extended warranties. Inaccurate life prediction can cut heavily into this income stream. Under-prediction of the failure rate will lead to cost overruns while overestimating failure will mean lost business to competing extended warranty plans and the setting aside of funds that could instead be used for further product development. This paper will illustrate the capabilities and value that this new tool provides to the various functional units within an electronics manufacturing company.

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs,ADCs,and memory. They are susceptible to electrical,mechanical and thermal modes of failure like other components on a printed circuit board,but due to their materials,complexity and roles within a circuit,accurately predicting a failure rate has become difficult,if not impossible. Development of these critical components has conformed to Moore's Law,where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last four decades through reduction in transistor sizes creating faster,smaller ICs with greatly reduced power dissipation. Although this is great news for developers and users of high performance equipment,including consumer products and analytical instrumentation,a crucial,yet underlying reliability risk has emerged. Semiconductor failure mechanisms,which are far worse at these minute feature sizes (tens of nanometers),result in higher failure rates,shorter device lifetimes and unanticipated early device wearout. This is of special concern to users whose requirements include long service lifetimes and rugged environmental conditions,such as aerospace,defense,and other high performance (ADHP) industries. To that end,the Aerospace Vehicle Systems Institute (AVSI) has conducted research in this area,and DfR Solutions has performed much of the work as a contractor to AVSI.
Physics-of-Failure (PoF) knowledge and an accurate mathematical approach which utilizes semiconductor formulae,industry accepted failure mechanism models,and device functionality can access reliability of those integrated circuits vital to system stability. Currently,four semiconductor failure mechanisms that exist in silicon-based ICs are analyzed: Electromigration (EM),Time Dependent Dielectric Breakdown (TDDB),Hot Carrier Injection (HCI),and Negative Bias Temperature Instability (NBTI). Mitigation of these inherent failure mechanisms,including those considered wearout,is possible only when reliability can be quantified. Algorithms have been folded into a software application not only to calculate a failure rate,but also to produce confidence intervals and lifetime curves,using both steady state and wearout failure rates,for the IC under analysis. The algorithms have been statistically verified through testing and employ data and formulae from semiconductor materials (including technology node parameters),circuit fundamentals,transistor behavior,circuit design and fabrication processes. Initial development has yielded a user friendly software module with the ability to address silicon-based integrated circuits of the 0.35um,0.25um,0.18um,0.13um and 90nm technology nodes.

Cost reduction in electronic assembly and soldering is a key issue for economic survival in the global market. Very promising
ways to reduce failure costs and increase productivity are: reduce solder paste bridging and reduce soldering failure modes
caused by insufficient solder paste depots. Increase line Productivity by reduction of cleaning frequency in the stencil printer. Nowadays highly sophisticated nano-coated laser cut stencils show an increasingly significant role in electronic production. The potential of nano-coated stencils is demonstrated with extensive printing experiments and is shown in this paper,
especially for critical area ratios. The stencil design was build up on BGA´s and QFP-structures with an area ratio going
down to a value of approximately 0,4.
The coating process is based on a Sol-Gel process and is followed by a temper process to start a multistep polymerisation.
The reaction layer is responsible for the high chemical- and mechanical resistance and provides the stencil with a high antiadhesion effect with a low surface energy. The coating is applied on the bottom side of the stencil and in the aperture walls.
The nano-coated surface offers a high functional surface with hydrophobic character and minimized adhesion of the solder
paste which results in a high efficiency of the printing process with a significantly reduced failure rate. An additional advantage of the nano-coated stencil is the reduction of cleaning intervals of the stencil bottom side due to the fact,that the adhesion of the solder paste to the stencil is dramatically reduced. Cost saving for less cleaning material is obvious and goes hand in hand with higher production line efficiency.
Further the paper shows the significant increased freedom of design rules due to the fact of smaller area ratio.