SMT rework machines are vital tools to many production engineers. They can be used to correct process errors and
repair test failures. They can also be used to service and upgrade products returned from the field.
Rework machines come in many forms – from the basic hot air type to complex laser and infrared heating units.
Whichever form they take,they have a common task - to deliver focused heat for the removal,replacement or
repositioning of SMT electronic components.
This paper discusses the need to control these systems on a daily basis. It addresses current methods and will offer
some alternatives and improvements. Finally,it suggests a statistical regime that will ensure machines are operating
in a controlled manner.

Current circuit board designs,particularly those in telecommunications,are so densely populated that they do not
provide enough clearance between SMT components and through-hole components to allow assemblers to use
traditional soldering methods. Clearances of less than 0.5mm (0.020”) are typical in these designs. To provide
assemblers with robust,repeatable selective soldering processes,equipment manufacturers have been challenged not
only to miniaturize the traditional flux-preheat-wave process,but also to add sophisticated positioning,motion
control,and optical recognition systems. This paper describes the many selective soldering challenges encountered
by assemblers,the current state of the art in automated selective soldering,and the future of this technology.

Wave and reflow soldering are well known,successfully proven mass soldering techniques. They offer the ability to
solder printed circuit boards in high volumes quickly with low defect levels,producing high quality solder joints.
Other available soldering techniques (e.g.,vapor phase,laser and hand soldering) are limited in terms of throughput.
Continued trends toward miniaturization in printed circuit design and assembly are resulting in increasingly more
surface mounted devices on the board,finer pitches and overall less space. Between the SMD components,however,
there remain,on many assemblies,a small number of through-hole components that either don’t have SMD
counterparts or are unique,or are there for other reasons. Selective soldering machines are typically used in the
production environment to solder these components.
This paper concerns the selective soldering process,wherein a robot is employed to bring circuit boards in contact
with the solder in order to individually solder through-hole components to the board. Other selective soldering
processes employ soldering tools mounted beneath a conveyor system. Except for the tools (e.g.,fluxer and solder
nozzle) that are different from the wave soldering process,these processes have nothing truly new to offer that may
benefit board designs. A robot system implementing a soldering process enables the use of new techniques that offer
the ability to solder different parts of boards,or even boards themselves,to another. This paper seeks to address the
possibilities of this process for mass soldering and tries to identify the limits of the process and its parameters.

The use of laser technology has found increasing applications in the electronics assembly industry. This non-contact
heating technique is ideal for components that require careful handling which otherwise might be damaged due to
the joining methods currently used. The main focus of this research effort is to evaluate the use of lasers as an
alternative energy source to attach flexible circuits to rigid boards. A designed set of experiments is performed to
optimize the different identified factors. The variables include different base materials for the flexible circuit,flux
chemistry,solder alloy,and operating parameters on the laser soldering machine. Various low-cost base materials
are identified and their performance is evaluated by performing strength tests on the joints to evaluate their
robustness. Further analysis included X-ray inspection for voids and cross-sectioning.

In both the server and portable electronic markets,monotonic mechanical overstress has become a primary issue in
manufacturing and field usage. Appropriate test methods,including four point bending,can be used for pro-active
design optimization.
The mechanical margin of safety in electronic assemblies has been decreasing over time. This is in part due to larger
component body sizes,increased PWB thickness,and reduced component stand-off. Identification of mechanical
fragility is important to assess the failure risk during manufacturing and field usage.
This paper will describe a four point bending test method utilized to examine the critical variables that influence
component failure levels. Testing was done on multiple package types mounted to two different PWB thicknesses.
Many components showed significant resilience to bend loading. Failures at different strain rates showed a
correlation between strain rate and monotonic failure point.

To meet the complex design requirements of the electronics industry,there is an increased need for large size high
I/O BGA packages. The size of these large BGA packages (up to 50 mm2 and 1157+ I/O) creates additional
manufacturability and reliability challenges. To ensure the success of these packages in manufacturing,the EMS
companies are providing manufacturability and reliability assessment services.
The influence of package size,substrate type,die thickness,Solder Mask Defined (SMD) vs. Non Solder Mask
Defined (NSMD) BGA pads,and board thickness on the board level reliability results are investigated. The
empirical test results from the Accelerated Thermal Cycle (ATC) are used to build the Finite Element Analysis
(FEA) model which allows an accurate projection of the board level reliability of similar BGA packages in various
designs. Cross Section,SEM,EDX,and Dye Penetration techniques are adopted to study the failure modes of solder
joints induced by the destructive thermal stress tests.
This study has demonstrated that board level reliability assessment conducted at the early stages of product
development is a valuable resource and can be used to ensure proper choice of components and enhance product
manufacturability.

Electronic package size reduction and demand for increased functions within less board space make a challenge for
the PCB designer to find smaller footprint components that will out perform larger sized components. The signal
density of electronic products has pushed the need for higher i/o count Ball Grid Array’s (BGAs) with smaller pitch
to be used for the transfer of signals in multi-layered PCB’s. These high pin count BGAs require excellent design for
manufacture rules along with very tight process controls to deliver a robust finished product to the marketplace.
This paper describes a PCB Test Vehicle that was used to test both the Design For Manufacture (DFM) guidelines
and the Process Controls implemented. This co-development project was to validate the design,assembly,and
process control parameters associated with using high pin count BGAS. Launching a new product using this
technology requires a joint effort to ensure “First Time Right “release and deliver the best time to market with a
robust assembly process.
The project was developed to test all aspects of the assembly process from double sided reflow process,single sided
reflow with cure process,selective wave solder process to standard wave solder processes. The goal was to
determine if there was a preferred process flow for using this new technology and if it could handle different
processes without any direct effect on functionality or yield.
Data was collected on component warpage,various temperature exposures,and their effects on the quality of the
solder joint. Visual inspection,Scanning Electron Microscope (SEM),Backscatter Atomic Number Image Contrast
(BSD) and Energy Dispersive X- Ray Analysis (EDX). Multiple EDX spectra were examined and the images were
recorded for the project.

Solderability testing is carried out at the IC (Integrated Circuit) manufacturer’s end to evaluate the quality of the IC
package terminals in terms of solder wetting ability. Current industrial standard procedures for solderability
testing—such as MIL-STD-883E and EIA/JESD22-B102-C—cover testing procedures for peripheral leaded
package types only. With the electronics industry’s recent moves towards lead-less packages and Pb-free soldering
processes,solderability issues of package terminals have become even more prominent,and universally accepted
procedures and standards of solderability testing for BGA (Ball Grid Array) packages even more urgent.
This paper describes process methodologies and their qualifications for solder joint strength and solderability tests
for BGA packages at PCB (Printed Circuit Board) level. These methodologies focus especially on BGA package
types with eutectic solder ball input/output terminals—e.g.,PBGA,Micro-BGA,FBGA,CSP,etc. Criteria taken
into account when developing the respective test methodologies included that they be practical and could be carried
out using standard SMT (Surface Mount Technology) processes and equipment. This paper concludes with
recommendations for 2 particular methodologies that proved to be the two most effective and reliable methods of
solderability testing of BGA packages on PCB board level.

With the increasing demands of complex functions in a single chipset or microprocessor,the development of large
size high I/O Flip Chip BGA (FCBGA) package becomes very important in recent years. In general,the component
suppliers will study the package level reliability data before they release the new components into market. To ensure
the quality and reliability of the products in the market,it is essential to study the board level reliability data instead.
In tradition,Accelerated Thermal Cycles (ATC) test is a widely accepted reliability test method in the electronic
industry. However,the ATC test is expensive and time consuming. It is necessary to adopt an efficient test method to
evaluate the board level reliability data for a new package design. This paper adopts the bend test technique
associated with the strain gauge measurement to learn the board level reliability data of a new designed package
under mechanical stress. Shock and vibration tests are performed to understand the product reliability under
shipping and handling environment. The shadow Moiré technique is used to study the component warpage under
different temperature points in the reflow process.
This paper presents an efficient model to study the board level reliability data for a new designed package. The
model can be used as a quick pre-qualification test and reduce the time to market of a new designed package. Some
of the tests specially designed to investigate the durability of the test component are also addressed.

In the present study,a simplified analysis methodology is used to evaluate thermal fatigue damage of solder joints of
a leadless ceramic chip carrier (LCCC) or a leadless chip capacitor/resistor (LCC/LCR). During temperature
cycling,only the solder joints experience elastic-plastic deformation while the rest of the assembly components,
such as the package case and printed wiring board,are assumed only to be elastically deformed. In the analysis,the
equilibrium of displacements of electronic package assembly is used to calculate the solder strain during temperature
cycling. This solder strain is then iterated according to the stress-strain behavior of solder until the solder strain is
consistent with the effective elastic modulus used in the analysis.
A thermal fatigue life prediction model,evolved from an empirically derived formula with some modifications,is
established. The analytical results,previously obtained from an experimentally validated fatigue life prediction
model and finite element analysis (FEA),combined with the derived solder strain are used to calibrate the proposed
model. In addition,the predicted lives calculated from the calibrated model match test results of 20-,28-,and 68-pin
LCCC packages,provided by JPL/NASA. Since this calibrated model is remarkably simple compared to the
evaluation with FEA,it is therefore recommended that this model serve as an effective tool for making a preliminary
determination of the solder joint integrity of LCCC/LCC/LCR during temperature cycling.