One of the factors that has contributed to the establishment of the Ni-modified Sn-Cu eutectic as one of the major alternatives
to the widely promoted Sn-Ag-Cu alloys as an RoHS compliant lead-free solder has been its apparent fluidity at temperatures
close to its 227°C melting point. This fluidity results in the alloy behaving similarly to lower melting point alloys in which
tin dendrites start to freeze out at temperatures higher than the nominal melting point. This in turn has meant that the Nimodified
Sn-Cu eutectic can be used as a wave solder and a HASL alloy at process temperatures not much higher than those
that have been used with Sn-37Pb solder. More recently it has been found that this fluidity also permits the use of the alloy in
reflow soldering with peak temperatures around 245°C,which is in the middle of the range used with the Sn-Ag-Cu alloys
that have a nominal melting point 10°C lower. In a study reported at APEX 2005 it was found that the Ni addition has the
effect of suppressing the formation of pro-eutectic ß-tin dendrites in the cooling Sn-0.7Cu alloy and promoting solidification
as a true eutectic and it was inferred that it was because of this effect that the alloy exhibited good fluidity close to its melting
point. In the study reported in this paper the fluidity of the modified and unmodified Sn-0.7Cu alloys is compared using two
techniques recognised in solidification science. The Ragone method measures the distance that the molten alloy flows along
a tube,a situation which to some extent simulates through-hole penetration in wave soldering and metallography of the
resulting sample provides a further correlation between the observed behaviour and the resultant microstructure. The
Dendrite Coherency method provides a means of confirming the change in solidification mechanism to heterogenous
nucleation when the Ni is present. The results of these tests are consistent with observed positive effect of the Ni in
enhancing the performance of the Sn-0.7Cu alloy as a practical lead-free solder.

The widespread use of SAC-based (SnAgCu) lead-free solder paste drives the industry toward reflow profiles that are
considerably longer than those used for lead-bearing products. This is due to the narrower process window. The latter is a
result of the higher reflow temperatures on one hand and the limited thermal resistance of the current generation of electronic
components on the other.
The minimized process window requires a significant reduction of ?-T’s between the small and large components. The most
common way to minimize ? -T’s is to extend the soak or ramp before the reflow phase.
It is well understood that the thermal breakdown of most materials is impacted more by prolonged dwell times at higher
temperature levels rather than the temperature level as such. The consequence,for the solder paste,is the thermal breakdown
of the organic material resulting in the loss of the protective flux blanket,finally yielding inferior reflow performance.
Industry sectors that typically have assembly designs with major differences between small and large components have the
option to successfully reflow these assemblies in a Pb-free process with the use of nitrogen to protect the solderability of the
assembly.
Since electronics manufacturing is a cost-driven industry,however,the use of nitrogen is a highly undesirable cost factor.
This paper describes the development and implementation of SAC-base Pb-free solder paste for use in reflow-processes with
extended temperature profiles,but without nitrogen.
It explains the need for flux systems in this generation of solder paste based to incorporate organic materials of longer
molecular chain length. Thermal resistance studies show the advantages of these materials. Also,solutions for the enhancing
the mobility of these materials are provided,impacting the printing properties of SAC-based solder paste.

One of the reported problems in moving to lead free has been increased solder voiding. Current research indicates that paste
formulation,reflow profile and board finish,when selected carefully,can produce equivalent void performance to eutectic
tin/lead systems. A method of simulating solder void conditions under a chip using copper performs is described. These
methods,when combined with traditional BGA porosity testing,are used to study the influences of board finish,paste
formulation,reflow profile and atmosphere on the solder voiding phenomena. All of this work is done with the popular
SAC305 and SAC405 lead free alloys. Finally,there are solutions to lead free solder void formation and one less trade-off in
the global effort to replace lead bearing materials in electronic assembly.

Vacuum-condensation soldering is a new process,developed to combine the advantages of condensation soldering and
vacuum soldering. The lecture introduces the results of the project development,as well as the results from soldering of
assembly groups.

Beginning July 2006,the electronic industry will enter the age of lead –free assembly and products in Europe. The removal
of lead from electronics brings massive changes for all companies in the supply chain,OEMs and contract manufacturers.
Lead Free SMT assembly poses many challenges for soldering and reflow processes. It requires significant process
optimization efforts to perform high volume manufacturing successfully and get good,reliable solder joints. Migration to
lead free assembly requires careful balancing of bill of materials with reflow profile. Double sided reflow requires careful
balancing of delta T from Side A to Side B reflow.
Cellphone assembly requires the use of thin form factor PWBs to meet the drive for miniaturization and thin,light products.
This is accomplished by using HDI- high density interconnect boards or build up technology boards. [1]. These PWBs have
stacked microvias,which are laser drilled and plated. The switch to lead free assembly requires the use of higher reflow
temperatures,so evaluation of the microvia connections after reflow is critical after assembly.
Solder joint reliability evaluations have to focus on Ball Grid array solder joint integrity,SMT packages,passive components
and connector solder joints. Rework processes are an essential part of the reliability evaluations as higher peak temperatures
for rework may affect PWB laminate,near neighbor components and package integrity.
This paper presents the results of lead free solderability qualification conducted at Kyocera-Wireless Corporation. The report
summarizes the results of X-sectional analysis,shear testing,thermal shock and temperature humidity testing of lead free
assemblies using a HDI board.
The paper summarizes the surface mount assembly evaluation conducted to ensure the stability of the laminate and microvias
through the double-sided reflow process and rework. This was evaluated as a part of the phone product qualification build.

The challenges for today’s PCBs are many,including higher assembly temperatures and higher device heat transfer
temperatures; faster clock cycles and higher bandwidths; higher component density; lower noise margins and high current
carrying requirements; while maintaining or improving cost/performance ratios and increasing assembly yields and field life.
This paper presents the work in Teradyne to characterize and qualify new printed circuit board (“PCB”) dielectric substrates
(a.k.a. “laminates”) to meet the requirements of lead-free assembly,while providing more reliability and flexibility to design
engineering. The paper provides details on: A) the drivers and the objectives of the program; B) some key properties of the
laminates selected for testing; C) the tests and the results; and D) some discussion and conclusions.

Dross generation has always been a costly issue for the electronics assembly industry. At least half,and in many cases,more
than half of the metal (solder) purchased for electronic manufacture is wasted as it becomes tied up in dross. With the advent
of lead free solders the moderate economic pain of dross generation becomes acute. A new process recently introduced to the
industry cures virtually all problems caused by dross.
This paper will show the true cost of dross,including metal replacement,loss of efficiency,and safety as well as
environmental issues clearly demonstrate a need for a solution to this problem. In addition to dross elimination the process
has been shown in the lab to reduce temperatures for wave and selective soldering and to improve wetting. Collaborating beta
test as well as lab test data will be presented along with initial actual production results.
In addition to answering the technical questions,why and how the “economics of dross” will be examined and a specific and
significant cost savings scenario will be presented.

Today,there exists a major push towards lead free soldering in the international electronics industry. It has presented a
number of challenges in both the surface mount and wave soldering processes. The conversion of assembly processes to lead
free from conventional tin/lead has put a strain on the smaller contract manufacturers in North America due to the perceived
need for improved production equipment. This includes recommendations for wave solder upgrades,reflow ovens with
seven or more heating zones,and repair equipment with improved preheating capabilities. These improvements require
capital investment that many smaller contract manufacturers cannot afford in the current electronic economic climate. This
paper details the development of a no clean lead free solder paste designed to be used with small reflow ovens with four to
six reflow zones. The paper will review flux chemistry,and recommended oven settings and modifications. The conclusion
is that there are viable lead free reflow soldering options that can be implemented with existing equipment and the process
will continue to improve as companies gain more experience in the subtle differences between soldering with tin lead and
lead free alloys.

During the design phase of a project,distribution of metal on the external layers of printed circuit boards is not a
consideration. System designers concentrate on implementing the required logic. PCB designers have to satisfy many
electrical and mechanical constraints and they do not lay out boards to provide an even distribution of metal on external
layers. This creates a difficult problem for the fabricator,who tries to evenly plate a board with uneven metal distribution. In
high-speed boards,uneven plating creates uneven impedance and circuit timing margins are decreased,negatively affecting a
circuit board’s performance.
In a plating tank,plating current is essentially constant across an entire panel being plated and all of the plating current must
be absorbed. Pads and tracks in an area of a board with low metal density will be plated more than the same pads and tracks
in an area of high metal density.
If a track originates in an area of high metal density and traverses an area of low metal density,its cross-section area will
change due to uneven plating. A change in cross-section area will produce a change in impedance and part of a signal
traveling along the track will be reflected. Reflections will cause a reduction in pulse amplitude,plus an increase in rise- and
fall-times. This will reduce circuit timing margins and may be the difference between a high-speed board working or not
working.
The best method of avoiding tracks with varying impedance is to equalize the metal distribution on external layers. Using
statistical analysis,the mean metal distribution is computed and thieving only added to areas below the mean to bring them
up to the mean. This provides a more even distribution of metal across a board,which will lead to better performance of highspeed
boards. Equalized plating will also make a board flatter,improving assembly yields.

Layout designers play a critical role in the design of high-speed circuits. In an optimized process,they take constraints
defined by engineering and create a layout that adheres to those design rules. Typically,however,the process is more ad hoc
with constraints being transferred via paper or voice,putting more responsibility on the layout designer to translate the
requirements and implement a functional design. In some organizations,engineering has taken over layout of high-speed
signals to ensure accurate implementation of constraints. Unfortunately,this often results in designs that are impossible to
complete or are un-manufacturable.
Today's complex designs can have advanced constraints on 80-90% of the board's signals,significantly increasing the layout
difficulty and design cycle time. To appropriately manage and implement these constraints,layout designers must
understand concepts such as differential impedance/signaling,star net topologies,interconnect delay and crosstalk coupling.
This paper will address:
• High-speed constraint categories in “electrical” and “physical” incarnations
• An optimized design process focusing on collaboration between engineering and layout departments
• Routing best practices to adhere to advanced high-speed constraints
• The impact/benefit of advanced fabrication technologies like HDI and embedded passives on high-speed design.