Surface mount assembly has dominated its through-hole predecessor since the early 1990s. The higher density and lower
ultimate cost of SMT makes it a preferred assembly technology. However,the mechanical strength of through-hole
connections continues to make through-hole the technology of choice in assembling connectors. This presentation will
describe the primary methods currently used for through-hole connector assembly: 1) selective wave solder,2) pin-in-paste
(PIP),1 reflow,3) hand soldering and 4) solder preforms. We will show how solder preforms are an excellent alternative when
PIP provides insufficient solder.
The wave solder method requires specialized equipment and processes to solder connectors. Pin-in-paste reflow evolved as a
way to accomplish through-hole assembly without additional equipment or process steps. In the PIP method,the additional
solder required to fill the though-hole barrel is deposited by overprinting the pad in the area of each connector pin,using
standard SMT equipment. During reflow,the solder wicks to each pin forming the solder fillet.
This paper explains why pin-through-paste reflow methods based on overprinting solder paste have become more challenging
due to an increasing use of Organic Solderability Preservative (OSP),fine-feature devices (e.g. fine pitch connectors) and
densely populated PCB layout designs that conflict with requirements for successful use of step-stencils. This paper also
shows an example where solder preforms were used to provide extra solder volume for each pin. This work demonstrates
how solder preforms provide a viable manufacturing solution to ensure complete through-hole solder joints.

Solder preforms are precise shapes of metal,produced by the high-speed stamping or forming of solder wire or ribbon.
Preforms provide a highly repeatable volume of solder,with 100% metal content by volume. They are commonly used in
conjunction with solder paste to incrementally increase the volume of solder joints,which increases reliability in connections
subject to mechanical fatigue,and increases signal-to-noise ratios in interconnections delivering high frequency signals.
Dozens of OEM and contract assembly houses have realized that the use of solder preforms can solve issues related to
inadequate solder volume in SMT processes. As with the adaptation of any new technology,issues arise and are resolved as
the technology evolves into mainstream,high-volume production. Over the past two years of process evolution,the most
common issues related to the implementation of perform assembly have been associated with high speed placement.
Although the preforms are placed in a similar fashion to chip components,they have suffered higher pick error rates than chip
components .
A series of studies were undertaken to understand the factors that influence pick error rates. This paper reviews the
experiments that studied standard shapes,unique “super flat” geometries,component orientations,and machine feeder and
nozzle selection. It also discusses the effect of preform shape and size tolerances,and compares the geometric specifications
to those of chip components.

Environmental regulations are forcing the elimination of lead (Pb) from electronic equipment. Solders containing lead have
been the standard in printed circuit assembly processes. Lead-free solders currently being used and developed for printed
circuit assembly require higher processing temperatures that can degrade the base materials commonly used in printed
circuits,resulting in decreased long-term reliability. Following a brief discussion of the regulations and lead-free materials
and processes,this paper will discuss several base material properties and present test data that highlights the importance of
specific properties that should be considered when selecting materials for lead-free applications.

A new set of constitutive equations for a class of lead-free solder alloys,Sn(3.5-3.9)wt%Ag(0.5-0.8)wt%Cu is proposed in
this investigation. These equations are applied to a 256PBGA (plastic ball grid array) package assembly. The creep results in
the PBGA solder joints are compared against those with other constitutive equations reported in the literature.

Applications using flip chips in high temperature and high current designs have increased in recent years,and this trend is
expected to continue. Markets utilizing these designs include high performance ASIC,high frequency/RF,and mid I/O
products. The migration of flip chip use into these designs can be attributed in part to the improved solder bump thermal
fatigue life which has been realized with the use of underfills,as well as to smaller final metal pad/passivation openings
being used by IC manufacturers. The need to use flip chips under harsher operating conditions has prompted work to address
reliability concerns with several diffusion related failure mechanisms. These concerns have surfaced in response to results of
high temperature storage (HTS) and high temperature operating life (HTOL) tests. In HTS tests,UBM (Under Bump
Metallurgy) consumption has been observed. In HTOL tests,UBM consumption as well as solder and UBM electromigration
have been observed. On flip chips with a bump structure utilizing eutectic 63Sn37Pb over a sputtered thin film Al-NiV-Cu
UBM,the HTS and HTOL reliability is a function of the UBM thickness – increasing the UBM thickness can have a positive
effect on reliability. However,in general a thin film UBM provides better bump thermal fatigue life,excellent protection to
the underlying aluminum,and is less likely to cause silicon cratering or passivation cracking.
A new approach to increasing the UBM thickness and thereby improving flip chip reliability regarding diffusion related
failures (while maintaining thin film characteristics),is to use an enhanced eutectic SnPbCu solder bump containing a small
amount of Cu in the 1% - 3% range. During bump reflow,the Cu in the enhanced eutectic SnPbCu solder bump has been
shown to precipitate out along the UBM/Solder interface,effectively forming a thicker UBM. This effectively thicker UBM
has been shown to extend the performance life of the structure in HTS and HTOL testing as compared to 63Sn37Pb while
maintaining equal performance in thermal fatigue life as evidenced by thermal cycle (TC) testing. This paper presents data
showing the increased reliability performance of the enhanced eutectic SnPbCu bump structure as compared to 63Sn37Pb.
Assembly and manufacturing characterization data demonstrating the excellent quality and manufacturability of the SnPbCu
bumps is also presented.
The liquidus temperature of SnPbCu alloys increases with increasing Cu %. Increasing Cu % beyond a certain level would
necessitate increased process reflow temperatures. Tests indicate that for purposes of wafer bump and circuit board assembly
reflows,enhanced eutectic SnPbCu alloys in the range of 1% - 3% Cu can be processed using standard eutectic 63Sn37Pb
reflow profiles. Data is presented showing that alloys within this composition range provide significant reliability benefits.

Electroplated pure tin and tin alloys such as Sn99.3Cu0.7%,Sn98%Bi2% and Sn96.5%Ag3.5% have been identified as
viable drop-in replacements to tin-lead solder. High melting point tin alloys such as Pb97%Sn3% and Au80%Sn20% are also
required by the electronics industry for flip chip applications. Capabilities of the commercial pure tin bumping chemistries
will be discussed and demonstrated.
However,commercially feasible plating systems for lead-free tin alloys have yet to be developed. The major difficulty in
plating tin alloys comes from the large difference in standard deposition potential of tin and the alloying metals that result in
poor alloy control and immersion of alloying metals on tin parts and anodes. Enthone Inc. has developed new processes that
allow robust and reliable electroplating of these alloys. We also studied the effect of plating parameters (current density,
agitation,temperature,etc.) and alloy composition on the materials properties of deposited alloys such as voiding,bump
height uniformity across a wafer,reflowability,phase composition,structure,hardness and melting temperature. A few defect
types specific to bump plating and ways to overcome them will be discussed. Recommendation will be made on utilization of
specific finishes for different electronic applications.

There has been much recent interest in printing solder paste onto UBM pads of a wafer. Usually the wafer pad is overprinted
using a stencil aperture that is larger than the wafer pad. This permits optimum bump height after reflow. There is also
interest in printing solder paste onto flip chip pad sites on a substrate such as Fr4 or Ceramic.
This paper will examine stencil aperture designs for bumping applications. The test substrate contains 2 groups of pads;
Group 1 has 4 mil (100-micron) pads on 10 mil (250-micron pitch),Group 2 has 4 mil (100 micron) on 14 mil (350-micron
pitch). Group 1 is divided into 5 sectors of 400 sites per section. The stencil has 5 different aperture sizes for Group 1 ranging
from 5.5 mil (140 micron) to 7.5 mil (190 micron). Group 2 has aperture sizes ranging from 8 mil (200 micron) to 12 mil
(300 micron). AMTX Electroformed Stencils 1.5 mil (38 micron),2.0 mil (50 micron) and 2.5 mil (63 micron) thick are used
to print the Group 1 and Group 2 apertures. Bump height after reflow will be reported for each Group and compared to
theoretical Bump Height and Print Area Ratios.

A conceptual framework for a new type of flip chip attachment is proposed. Gold stud bumps are provided on the chips,and
wells filled with solder paste are provided on a flexible substrate serving as the system board. Pushing the stud bumps into
the wells provides a bump/well connection,and heat is applied to melt the solder and make a permanent connection. An area
array of bump/well connections can have a pitch of 100µ or less. The connections are projected to be mechanically robust,to
support operating frequencies of 10GHz and above,and to support replacement of defective chips as many times as
necessary. Imprinting provides a fabrication method having sufficient precision to shrink the trace and dielectric feature sizes
by a factor of around 20 compared with conventional FR-4 boards,while still maintaining 50O traces. The same precision is
used to eliminate redistribution layers that are normally required between the fine pad pitch of IC chips and the coarser pad
pitch of a conventional board. By also using imprinting to fabricate the wells,a low assembly cost is achievable,potentially
below 0.06 cents per lead. This compares with an industry cost as high as 2.5 cents per lead for performance flip chip
PBGA1. The most advanced materials can be used including copper conductors and Cytop2 as the dielectric. At 10 GHz,
Cytop has a dielectric constant of 2.1 and a dissipation factor of 0.0007. The proposed manufacturing methods and assembly
techniques can be applied to a broad range of microelectronic systems including high performance circuit boards,high
density cables with controlled impedance,integrated passives,and stacked die packages.

Use of solder paste as a material to bump silicon wafers for interconnection to other level of package interconnection is a
simple and cost effective process. However,the material properties of the paste become critical if the quality of the bumps is
to be consistent. Especially critical for high bump quality are low solder balling and low void formation during paste reflow.
Work at Kester Northrop Grumman has shown that flux material properties and powder morphology influence both the
formation of voids and solder balls. This paper will describe a series of experiments that allowed an understanding of these
two major problems. Follow up experiments resulted in a paste that was optimized based on flux composition and powder
morphology.

Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller,lighter,
and less expensive packages,and flip chip is an important enabling technology for these product trends. Underfill between
the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill
dispense and cure step is not a typical process for an SMT factory,and demands additional capital equipment,floor space,
cycle time and headcount.
An alternate approach to traditional capillary underfill is wafer applied underfill. The underfill is applied after wafer bumping
and sawing,but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly
processes. Liquid-to-liquid thermal cycle shock tests (-55oC to +125oC) have been performed on test vehicles assembled with
the wafer applied underfill. First failures were over 1000 cycles. Weibull plots of the data are presented.