Reliability testing applying surface insulation resistance (SIR) measurements to materials that are used for electronic devices is a fundamental task in the automotive industry. SIR measurements based on the B52 test board (IPC-9202) was further developed with a derivation of a mathematical tool allowing the prediction of ECM failures on the ppm level. The underlying equations are based on SIR measurements that were carried out under step-load conditions for different material combinations on B52-PCBAs. It could be shown that the SIR level and its scattering in repetitive measurements is a clear indicator for the ECM risk, depending on the local humidity. The set of equations based on design of experiment (DoE) evaluations were set up in a way so that a risk factor can be calculated as a function of design, applied voltage, local humidity, and applied assembly materials of the PCBA. In combination with statistical methods, this mathematical model allows, in a practical way, to predict the risk of ECM failures. It can calculate expected ppm failure rates from humidity load collectives which can be obtained from operational conditions of electronic control units in the field. The approach thus represents a new module in reliability engineering of humidity-induced defects.

Server hardware is often interconnected with high-speed, insulated copper cables to transfer data several meters or more between other servers, network hardware, and storage devices within datacenters. Over the last few decades, data transmission speeds have increased significantly. As speeds have increased, the dielectric properties of electrically insulating cable jacket materials have become increasingly important to ensure adequate and reliable signal integrity for long-distance, high speed data transmission.

This paper details the failure analysis investigation of 40 Gb/s high-speed data transmission cables that began experiencing signal integrity issues four years after being manufactured. Failing cables were experienced high insertion loss (attenuation), which ultimately led to data packet loss and affiliated errors generated by the servers in which the cables were installed. Physical analyses were performed to determine root cause of the failures, including electrical testing, microscopy, Fourier-transform infrared spectroscopy, thermal analysis, aging studies, and rheology. These combined assessments proved that the failures resulted from degradation (reduction of molecular weight and oxidation) of the linear low-density polyethylene (LLDPE) wire insulation. During operation within the datacenters, the LLDPE wire insulation began to oxidize over time, causing an increase in its polarity and related dielectric loss properties. The increase in dielectric loss prompted a corresponding signal integrity degradation of the interconnected cabling paths and resulted in data packet loss during signal transmission. The overall insulation degradation was traced to an uncontrolled manufacturing process at the wire manufacturer. The failure analysis methodology and experimental results are presented in this paper.

The surface mount technology (SMT) process is well known and mostly measured in terms of efficiency, cycle time (CT) and first time quality (FTQ). Once the Customer’s needs are fulfilled (demand needs covered and FTQ meeting expectations), most companies feel comfortable enough to do the regular key process indicator (KPI) monitoring, guaranteeing the process is under control. Nevertheless, we must start to look deeper to find the “hidden losses”, so we can extract as much performance as possible from the process. The main goal of the SMT process is to add value by placing surface mount devices (SMDs) as fast as possible and with zero defects. To do so, it is a must to have the right technology and optimized placement machines, according the product specifications.

A certain SMT process might have a great OEE, higher than 85% and single digit ppm FTQ, but still not be fully using all installed capacity. If the total placement installed capacity is 150000 chips per hour (cph) and it is being used to place 100000 cph, it means a 30% loss of potential capacity. The components per hour metric (CPH metric) is poor in this example and leads to the “hidden losses”. Keep in mind that efficiency is still 85%, FTQ at single digit and customer demand are being met.

This paper will focus on the requirements needed to implement a central database for printer recipes and minimize setup time required to begin production. The SMT process works best the more we minimize the human intervention required. With electronic manufactures embracing the concepts of Factory 4.0, it has become clear that recipe control has become a vital element to maintain a stable and repeatable process. Removing recipes that are machine-based and implementing a central database has shown to improve overall quality and job-to-job repeatability. This capability has been available on equipment for years and the advantages known; however, the issue has been setup time from when the recipe is loaded until the product is running at acceptable results for both alignment and print results. This machine-to-machine variation has stifled the implementation and is often the cause of failure. The following paper will outline the steps to implement a central database recipe process and how to synchronize the individual machines to minimize setup and time to production.

SMT and electronics manufacturing industry experts are unanimously moving forward to have line controlling and automation in their digital transformation journey. Typical A typical SMT line formation consists of Solder Paste Printing (SPP), Solder Paste Inspection (SPI), Pick and Place machine (PnP), reflow oven, and Automated Optical Inspection (AOI).

Now, SMT manufacturers see the bigger picture on top of single automation solutions, such as better SPI yield or better AOI quality gate control checks. The new focus is to look at the entire line operation, utilizing digital solutions to eliminate pain points and address long-term operational strategic visions.

Line controller will act as a collaborative agent to orchestrate line processes, which consist of man, machine, material, and method (4M) elements. Line controllers intend to reduce complexity by coordinating and consolidating disparity in the line to enable machine-to-machine (M2M) communication for better productivity and quality control. Practical use cases:

• Multiple lines orchestration - Enable planning/dispatch teams to identify the most compatible line with the least effort for the next changeover run, where manual approach may take at least 1-2 hours for data review and to get the optimum line to perform conversion.

• Central monitoring and controlling - Improve mean time to resolution (MTTR) of the line. Without such an approach, operators need to be on standby at each SPI, PNP, and AOI stations.

• Integrate machine, recipes, and material information - Optimize material stock planning to enable just-enough materials to start the line and just-in-time material replenishment. In high mix productions, material preparation into consideration with 4-6% material buffer to reduce possible logistic time loss between production and warehouse.

• Smart changeover - Auto recipe download for the next lot recipe in queue and informs operators to perform the changeover.

• Flexi line formation - Configure new machines into a single orchestration platform (line controller) instead of multiple, siloed applications.

• PCB eMap interchange – Detailed PCB data collection and avoid unnecessary material consumption. With assumption of 98% yield from SPP, it is possible to save 2% of unnecessary material consumption at the PnP.

The surface insulation resistance (SIR) of conformal coatings was investigated using increased stress by high voltage bias up to 1000V. Test boards had been prepared according to IPC-9202, using components withstanding high reverse bias voltage. Pads arranged in comb structures had been added to assess different creepage distances according to IEC 60664-3 and IPC 2221B.

The electrochemical performance was tested by a SIR test at different bias voltage levels from 500V to 1000V, at static humidity condition of 65°C/93% relative humidity (RH), for a duration of 1000h. The sequence was followed by a damp heat test under the same bias condition, according to IEC 60068-2-38 without frost phase. The effects of the increased voltage stress on the surface insulation resistance were investigated according to the creepage distance and the withstand voltage level of the components.

A positive influence of conformal coating protection on the electrochemical reliability under higher voltage bias was shown. Conformal coatings show a potential to reduce creepage distances under the protected areas, if the material combinations of printed circuit board (PCB) materials, soldering process, and conformal coatings are compatible.

This procedure can be a basis of electrochemical reliability testing of PCB assemblies for elevated voltage requirements.

Polymeric conformal coatings are used to improve and extend the reliability of printed circuit boards against environmental conditions. There is high interest in using light-curable conformal coatings due to their process benefits over conventional technologies, including the ability to use a non-solvated 100% solids material, higher throughput, space savings, and lower operating costs. Light and moisture dual-curable conformal coatings were developed to ensure the curing of the coating even if the material flows underneath components on circuit boards. The use of light-curing coatings in aerospace and defense applications has been limited due to stringent low ionic content (MIL-STD 883 method 5011.7) and low outgassing (ASTM E595) requirements. A recently developed technology enabled formulation of a coating that meets these requirements without giving up the process benefits of the light and moisture dual cure conformal coatings. In this paper, the ionic content, outgassing, and reliability testing, such as, heat and humidity (85oC, 85% relative humidity), sequential thermal shock and cycling (-65oC to +150oC), and salt spray corrosion resistance will be discussed. These results are compared against “out-of-kind” conventional conformal coatings used in the aerospace and defense industry and an “in-kind” light and moisture curable conformal coating.

In the latest IC substrate PCBs, via holes have downsized and these diameters have minimized below 10μm, which have led to the issues of connection reliability. In a conventional process, adhesion failures have occurred between inner copper layer and plated copper films in via holes because the direction of copper crystals changes and nanovoids exist at the interface of electroless copper plating. To align the direction of crystallized copper in via holes, the thinning of electroless copper plating is effective; however, the reduction of thickness can cause a low covering power and the increase of the resistance values in the conventional process.

Concerning the process newly studied, we succeeded to solve the problem of the covering power by controlling the growth of electroless copper plating at via surface and via bottom respectively, and to inhibit a rise of the resistance values by increasing copper purity. The observation by backscattered electron images in field emission scanning electron microscope verified that the crystallized copper aligned toward the same direction at via bottom in the new process. From the results by solder heat resistance test, no adhesion failures were found and improving via connection reliability was proved in the new process. This work demonstrates that the new process can make the thinning of electroless copper plating possible and can align the direction of the crystallized copper between the inner copper layers and the plated films; consequently, the improvement of via connection reliability is achieved by thinning electroless copper plating.

IPC J-STD-004B standard prescribes general requirements for the classification and testing of soldering flux for high qualify interconnections. This standard defines the classification of soldering materials through specifications of test methods and inspection criteria. The materials include liquid flux, paste flux, solder paste flux, solder preform flux, and flux-cored solder.

This research will use the proposed IPC-53 Surface Insulation Resistance (SIR) test patterns by means of an open comb (2D) and closed comb (3D to simulate a component over the comb pattern). The 2D open comb has uniformity of conductor spacing, sheet resistance, and flux outgassing. The 3D-closed comb simulates the effect of leadless or bottom-terminated components, which have non-uniform sheet resistance and flux outgassing.

The response variables will include SIR testing and visual imaging. The objective is to investigate IPC test method improvements for characterizing soldering fluxes using leadless components with narrow pad-to-pad spacing.

Crimped electrical contact reliability is controlled through strict manufacturing processes and verifications, including pull force testing. Cable and wire harness assemblies’ standards provide the minimum pull force for reliable cables. However, in practice, failures occur at a much higher tensile strength than the minimum required.

The first section of this paper reviewed 780 pull force tests provided by NASA that were analyzed to determine how the data compare to NASA’s pre-existing requirements from cable/harness standards. The measured tensile strength of most of the contact/conductor pairs exceeded the minimum pull force values of NASA-STD-8739.4 and IPC/WHMA-A-620 by at least 100 %. The contact/conductor pair samples’ tensile strength followed a normal distribution with an average tensile strength that was at least 182 % of the minimum requirement, and all samples analyzed passed pull force testing. In addition, the 95 % confidence interval of the average tensile strength distributions for several contact/conductor pairs was plotted as error bars to show that the contact/conductor pairs will meet and surpass the requirements.

The frequency of pull force testing can be problematic for projects because of the cost and availability of spare contacts for the destructive test. It is possible to reduce the frequency of pull force testing if at the beginning of the production run, the conditions of the crimp tool and materials are verified, and the settings of the tool remain unchanged throughout the process. However, the project needs to evaluate the impact to risk from reducing the frequency of testing prior to implementing process changes.