This work compares the influence of a plating additive that has been applied to a commercially available electroless copper system and how its use impacts the morphology of the overall final plated structure. Through testing on insulating materials in addition to single and polycrystalline copper substrates, each electroless Cu solution is shown to be influential in suppressing grain growth in certain crystal orientations, which can lead to significant physical differences across the final plated interface. It is interesting to note that while the degree of epitaxy between the substrate Cu and the electroless Cu can be influenced dependent upon the additive utilized, this can occur independent of the impact between the electroless and electrolytic Cu. To wit, an epitaxial interface between the substrate and electroless Cu is not strictly indicative that an epitaxial structure will occur between the electroless and electrolytic Cu.

The plating additive under investigation is shown to support epitaxial or “bottom-up” recrystallisation for selective grain orientations originating within the substrate material and will typically facilitate grain growth in the (100) and (110) orientations while a solution without the additive supports the (110) and (111) orientations. Such performance is offered as occurring as a result of the characteristic electroless copper surface which consists predominantly of large, but low index {100} facets, in contrast to the smaller but higher order facets {221} that occur when the additive is not employed. When applied to polycrystalline substrates, either of the electroless copper processes considered within this investigation have been shown to facilitate a fully epitaxial structure, which arises from the situation that either of the “preferred” crystal orientations are available within the substrate.

Through careful selection of the additive packages used within an electroless Cu system, there can be significant control gained over how not only the electroless layer itself crystalizes, but also the response of the subsequent electroplated layer as well. Both of these are understood to have significant impact on the physical and mechanical properties of such an interface, which in turn can be influential in achieving the desired overall properties.

Through an increased understanding of how the additives used in a state-of-the-art electroless copper process function, and the impact that they subsequently have on the crystallography of the final deposit, it is anticipated that an improved overall joint integrity can be achieved. It is now considered that a fully epitaxial microstructure across the target pad – ELESS – ELYTC Cu interfaces is desirable as this offers a higher resistance to crack propagation and so enhances overall reliability. This is clearly beneficial in many plating applications, especially those containing microvias, where historically decreasing dimensions and aggressive operational demands in combination with an increased use of stacked BMV designs has led to undesirable interconnect failures around the target pad – electroless Cu – electroplated Cu interface.

The High Density Packaging (HDP) user group has completed a project to evaluate the impact on field reliability of more frequent thermal cycling over more narrow operating temperature ranges such as occur in today’s data center or cloud environments. In the past, printed wiring board field reliability testing assumed just one thermal cycle per day based upon systems begin completely shut off in the evening and circuit temperatures dropping to ambient temperature before being turned on again every morning. Whereas many systems today are rebooted and/or go into a lower power “sleep” mode ten or more times per day. In addition to the above new field application environments, laminate materials today have higher filler content and their mechanical characteristics are different from the less thermally robust phenolic and dicy-based laminate materials used prior to the widespread use of high temperature lead-free solder alloys in board assembly. Note that this project concerns the reliability of the bare printed wiring board and has no connection with any earlier “power cycling” projects which evaluated the reliability of various SMT or PTH solder joint alloys.

The goal of this project was to determine the relative impact on field reliability of more frequent thermal cycling over a more narrow temperature range with less frequent temperature cycling over a larger temperature range using at least two of the laminate materials available today. Interconnect Stress Testing (IST) is one of the recognized standards for measuring the expected reliability of bare printed wiring boards. Although there are other methods, the more practical IST method was selected for determining the impact of these new field conditions on printed wiring board reliability.

For both laminate material test lots, which had several physical differences, the results show that more frequent thermal cycling can significantly affect long term field reliability even with reduced temperature cycling ranges.

Failure of a printed circuit board assembly (PCBA) can occur because of design, manufacturing, mechanical, or electrochemical issues. A propagating fault is a severe failure mechanism in which smoke, electrical arcing, and/or thermal degradation occurs. This paper details root cause failure analysis of a PCBA propagating fault resulting from flexure-induced capacitor cracking. This investigation also included optimization of design and qualification practices to reduce the risk of flexural crack induced failures.

Multilayer ceramic capacitors (MLCCs) are susceptible to flexural crack failure resulting from high strain inducing events, like bending or warpage. The PCBA in this study includes an array of MLCCs that initiated the propagating fault. The MLCCs are in a high strain region of the assembly, which created a short circuit when the flexural cracks propagated across opposing electrodes. The strain level on the MLCCs was exacerbated by adverse warpage conditions and proximity to rigid mounting constraints. Dynamic strains were a contributing factor due to a partially unsupported module directly adjacent to the capacitor array. The dynamic stain on the MLCCs, combined with residual strain, exceeded the strain threshold for the capacitor. Root cause was confirmed through physical analysis and finite element analysis (FEA).

Root cause failure analysis included an assessment to prevent reoccurrence of capacitor induced failures. PCBA and system design factors were evaluated to improve quality and reliability. Future design recommendations were provided, including implementing capacitor spacing guidelines, evaluating layout/component placement to reduce warpage, and employing FEA modeling to evaluate high strain regions.

Fluororesins such as PTFE, which have excellent low-dielectric properties, are used as substrates for high-capacity, high-speed transmission, and their application is increasingly promising in beyond 5G and 6G society. However, a fabrication of multilayer PTFE substrate requires high-temperature pressing (about 350 °C), and its via fabrication is challenging. Against this background, a novel bonding film and thermoset resin has been developed for PTFE multilayer substrate using unique resin technology.. This bonding film has low-dielectric properties (Dk = 3.0 / Df = 0.0023 at 10 GHz) and high adhesive strength with PTFE substrate. Thus, this bonding film enables a multilayer PTFE substrate which maintains the low loss properties of PTFE to be fabricated under low temperature press (200 °C). In addition, due to its good desmear processability, blind vias with high connection reliability can located in multilayer PTFE substrate.

The search for novel adhesion promoters (AP) for inner-layer bonding of printed circuit boards that meet the requirements of high-frequency applications is driving the surface treatment industry away from established technologies and toward novel solutions that use chemical compounds as the primary source of adhesion. One reason for this is to avoid negative effects on signal integrity (SI) performance and minimize dimensions of the conductive path caused by etching and roughening the surface material to achieve mechanical adhesion to the substrate material. This change in technology leads to new challenges not only in developing viable adhesion promoters that are compatible with many substrates, but also in establishing appropriate quality control procedures for chemical bond coatings.

This study focuses on the characterization of a novel hybrid adhesion promoter that combines anisotropic nano etching with a chemical adhesion layer based on a self-synthesized silane compound. To determine its functionality, it is compared to established processes using laboratory and production data. Since the thickness of the adhesion promoter, introduced at the interface between the organic polymer and the copper substrate, can significantly affect its functionality, a suitable method for determining its thickness and distribution is reported. This nondestructive thin layer detection method will be discussed, establishing accurate correlation to its thickness measured by standard focused ion beam scanning electron microscope (FIB-SEM) techniques.