Different types of components with soldered bottom terminations are increasingly used in the electronics industry with the principal objective to improve heat dissipation.

The large areas of the solder terminals are an advantage for the heat to escape. However, if the thermal pad design is not optimal or the assembly process not properly adjusted, big voids could be created in these solder joints. The industry criterion for acceptable voiding for thermal pads wettable area is <50% for class 1, 2 and 3 [1]. But there is no established limit for unacceptable voiding, anything above 50% is treated as a “process indicator” for Class 2 and 3.

As heat dissipation improves with less voiding and single large voids may create hot spots, it is important to achieve as low voiding amount as possible and prevent large voids from forming.

There are many parameters that affect the amount of solder joint voiding. Optimization of the stencil design together with a good choice of solder paste, or solder preforms, and a good assembly process have the potential to significantly lower the thermal pad solder joint voiding and to increase the soldered area.

X-ray images of two typical Quad Flat No-lead (QFN) thermal pad solder joints generated from different solder pastes, but otherwise identical process setup, are shown in Figure 1 (shown in paper).

The actual design of the thermal pads is also important. In this presented study, different thermal pad designs to minimize voiding and maximize soldered surfaces for QFN thermal pad solder joints have been investigated.

The purpose was to find thermal pad designs for standard QFN packages that result in consistent solder joint voiding, well below the acceptable limit [1], and have as large soldered surface area as possible.

The Semi-Additive Process (SAP) is a standard process to enable very fine lines and spaces to produce highly sophisticated Integrated Circuit Substrates (ICS). When operating with lines and spaces (L/S) of less than 10/10 µm, the copper thickness variation is one of the critical parameters; it must be controlled within a tight range to avoid reliability problems in assembly or during the lifetime, as described in several papers [1, 2]. Also, new packaging technologies—like 2.1D and 2.3D—are requiring L/S in the rage of 2-5 µm for the Redistribution Layer (RDL), as shown in the examples in Figures 1 and 2 (shown in paper).

These new 2.1D or 2.3D packaging technologies do have much higher requirements on the electroplated copper than the ones deposited with the electrolytes used for PCB or standard IC substrates, with L/S of less than 15 µm. The new copper plating electrolytes and processes need to be able to fill the technology gap between current semiconductor technology and the current IC-substrate technology, as shown in the Figure 3 (shown in paper).

The challenges and requirements for such a new copper electrolyte to fill the gap between the organic IC substrate and the semiconductor technology are increasing more and more with the shrinkage of the L/S and the smaller pattern features on the substrate. The following characteristics of a new copper electrolyte are getting very important:

1. Excellent shape of lines/tracks

2. Blind Microvia (BMV) filling with low dimple

3. A very good within-panel distribution (WPD) of the plated copper

4. Surface appearance of the electroplated copper with low surface roughness

5. Excellent copper-crystal structure, ductility, and tensile strength to enable a good reliability

6. Possibility to plate at a high-current density to operate under low manufacturing cost

7. Cyclic Voltammetry Stripping (CVS) controlled dosing of electrolytes

8. Particle-controlled electrolytes (manufactured under cleanroom environments)

9. Controlled purity of the electrolytes (trace metal controlled)

Therefore, the continuity of innovation and invention as expected by Moore’s Law is needed also on the copper electrolyte side to reduce cost and increase capability to cope with the latest packaging technologies like 2.1D or 2.3D. Challenges like within-panel distribution become a critical factor for the subsequent processing steps.

This technical paper will contain results of copper thickness and the copper thickness variation also called within-panel distribution (WPD), microsection pictures, design of experiments (DOE) results, BMV filling performance, ductility results, and copper crystal structures of the new developed electrolyte. Finally, the chemistry has been further enhanced by producing it under semiconductor standards using high-purity chemicals and ultrafine filtration, tracing all by-products to have the utmost control of the copper plating chemistry. Such a new copper electrolyte was developed to cope with these challenges. All the characteristics mentioned above have been tested with the new electrolyte formulation. Because of the success of this new formulation, it is already used in more than 15 production lines worldwide..

The next generation devices using high frequency of 5G to mmWave and greater has called for innovation in materials used in electronics manufacturing to realize the optimum signal integrity and performance. The selection of materials is critical especially at the printed circuit board (PCB) level for minimized insertion loss. The right choice of surface finishes is paramount for signal integrity and overall reliability of electronic assemblies.

The novel surface finish with nano-engineered barrier layer-finished with an outermost gold layer has shown superior benefits in 5G-mmWave frequency PCB technologies. The technical evaluation of signal integrity at 5G-high band, mmWave and higher frequencies with novel surface finish comparing with alternatives will be discussed. Furthermore, reliability evaluation will be highlighted involving novel surface finish.

PCB Fabricators have long since abandoned Hot-Air Levelling, with several alternative final finishes (ImAg, ImSn, OSP, ENIG and ENEPIG) now well established as having a track record of meeting fabricators cost/performance requirements. As system designers continue to respond to new performance demands, it can be noted that ENIG/ENEPIG finishes have endured as a leading choice in many advanced applications where reliability is prioritized over cost.

Electroless nickel (EN) deposits have served well as a barrier layer preventing copper migration to the outer gold or palladium-gold surfaces, enabling the robust solderability performance of ENIG and ENEPIG finishes. However, with the recent introduction of the 5G mobile network creating growing demand for smart phones, networking, and wireless connections, all requiring increased “data flow”, the need to reduce the signal loss at higher frequency bandwidth is becoming vitally important. The low conductivity and magnetic properties of EN affect electrical signals as they travel along the conductor’s outer surfaces leading to insertion losses at higher frequencies.

As a result, fabricators are once again looking to newer generation surface finishes to meet their performance criteria. EPIG and Silver-Gold (AgAu), as well as reducing the EN thickness from traditional ENEPIG, have all gained some attention in recent times. This paper will review and compare the performance attributes of the leading candidates for a high frequency alternative surface finish

Aerospace and defense applications present unique challenges for material suppliers. As increasingly adoption of wide bandgap semiconductor materials and advanced diverse accessible heterogeneous integration technologies, power density of defense and aerospace devices increases rapidly. Traditional die attaching materials is becoming an increasingly limiting factor in microelectronics packaging for the next generation aerospace and defense systems.

This paper introduces an advanced die attaching material based on pressure-less silver sintering technology and epoxy-based adhesive technology. This die attach paste can be sintered at temperatures that are normal in typical die attach processes while delivering outstanding mechanical, electrical, and thermal performances. This paper presents the results of an application study aimed at developing this unique technology in the field of high-power density devices for aerospace and defense applications.

The rapid change to and steep rise of electric vehicles (EV) results in many challenges for the design, manufacturing, testing, and the understanding of reliability and robustness for printed circuit board (PCB) in automotive powertrain applications. The greatest change is that high voltage—up to 1000 Volt operating voltage—and several hundred Amps operating current is required. The high voltage is creating a very high electrical field in the PCB. In combination with the tight designs and the environmental conditions, there is a possibility of effects which can cause ionic migration and/or partial discharges, which lead to failures over time. CAF (Conductive Anodic Filament) failures can be observed already at low voltage where ionic migration appears along glass fibers or laminate borderlines. At high-voltage conditions with a respectively high electrical field, vertical failure can grow through the bulk resin material of a PCB, creating over time a short from layer to layer. This article shows the failure characteristic of such vertical high-voltage failures in PCB. Which conditions can lead to such failures in a PCB— considering design, stackup, manufacturing, and testing aspects—will be discussed. Solutions to reduce the risk in generating such failures are shown and discussed. For solutions to allow higher currents, it is essential to have good thermal pathways in order to get the heat out of the system. Combinations of such thermal solutions with the high-voltage robust PCBs are shown as system solutions.

“Light weighting” has become an important trend in numerous manufacturing divisions. Lightweight materials are particularly valuable in any portable device including mass transit systems, automotive systems, and portable tools. They provide a wide range of benefits including reduced fuel consumption required for transport, lighter materials minimize waste through material saving, reduce consumption of finite resources, reduce environmental footprint, and achieve cost saving. The ability to do more with less could be game-changing to electronics ruggedization. More and more organizations are committing to working towards a more sustainable future. Traditionally, conformal coatings and encapsulation resins are used as part of circuit board assembly to meet the performance challenges in a variety of electronic applications, such protective polymer materials are often essential to ruggedize a system and give much needed protection from harsh external environments and reduce negative impacts from long term wear-and-tear such as shock and vibration. Encapsulation resins are typically derived from crude oil and are heavily filled with mineral rock powders, and thus have a high density and contribute significantly to the weight of the overall encapsulated device. This paper presents a novel, bio-based, expandable, thermoset solution, a low density, light weight method to effectively encapsulate and protect electronic components.

The performance of low density, bio-based polymers, synthetic conformal coatings, and encapsulation resins is assessed using numerous accelerated life tests. Bare and reflowed TB33A test coupons were coated, and the Surface Insulation Resistance recorded at 85°C (+185°F), 85% Relative Humidity, to understand the impact high temperature high humidity has on electrical resistivity. Test assemblies with a variety of surface mount components were subject to short term Condensation Testing, the Insulation Resistance was recorded. The electrical performance of a novel Foam Topcoat ruggedization solution was evaluated by monitoring the Insulation Resistance of B-24 test coupons when completely immersed in water. This comparative study concludes that the proposed bio-based, expandable polymer acts as a lightweight solution to effectively protect an electronic device subject to harsh operating conditions, including high temperature high humidity and condensing environments. For underwater applications a novel Foam Topcoat ruggedization solution can be used to achieve a perfect scoring solution and achieve a significant weight reduction, greater than 80% weight saving is obtained when compared to traditional encapsulation resins.