The research goal was to establish a limit for the number of rework cycles for Ball Gird Arrays (BGAs) and to determine the clearance required between a BGA and its surrounding components on an assembly without impacting the overall Printed Circuit Board (PCB) and Printed Circuit Assembly (PCA) reliability. This project’s test vehicle is comprised of four different sets of layouts, each utilizing a large plastic of 40×40mm (1.6"×1.6") BGA surrounded by various sizes of BGAs—(3×3mm (0.1"×0.1"), 6×6mm (0.2"×0.2"), 6×8mm (0.2"×0.3"), 8×8mm (0.3"×0.3"), 9×9mm (0.4"×0.4"), 11x11mm (0.4"×0.4"), 17×17mm (0.7"×0.7")—placed at various clearances to the center BGA. The surrounding BGAs consist of various pitches, substrate materials, and package sizes, and are placed at specific clearances—1.3mm (50mil), 2mm (75mil), 2.5mm (100 mil), 3.8mm (150mil), 5mm (200mil), 6.4mm (250mil), 7.6mm (300mil), and 10mm (400mil)—away from the center BGA, which is the rework site. Peak temperatures were recorded using thermo-couples at the surrounding components during each rework cycle. Based on the drop shock reliability test results and cross section of microvias, PCAs were still reliable after two rework cycles as failures were not due to fatigue and via structures were still good and fully intact. Thermocouple results showed that a clearance of at least 10.16mm (400mil) is required for reduced effects of secondary reflow [1]. Examples of secondary reflow effects are the risk of increased void percentage (%), solder joint brittleness, hot tear defects, and PCB delamination. However, this may not be favorable to high-density designs. Nevertheless, secondary reflow is inevitable at all adjacent components due to physical proximity. Alternative soldering methods or physical shielding techniques [2] must be deployed for tight spacings; these will require further study.

Repair of soldered components is a constant necessity in the electronics industry. Product performance enhancement, damaged components, and exchange of wrong placed components are some of the motivations behind a repair. Dispensing and placing a 400 µm pitch component manually is very time consuming and could cause collateral damage to the already populated components. A novel automatic repair method and tools with no human interaction were developed. This method uses the advantages of solder jetting and pick and place in one instrument, making it extremely accurate, reliable, and cost-effective. The use of different alloys including low-temperature soldering (LTS) is feasible. The results show that this technique significantly improves the throughput of the repaired devices.

During the past few years, it has become increasingly difficult to physically rework printed circuit board (PCB) assemblies. Such mundane operations as soldering, desoldering and component replacement have become complicated by extreme micro-miniaturization, the use of lead-free solders, new thermally challenging PCB’s and intricate component packages, such as BGA's, QFN’s and other area array packages, that are difficult to install and remove. As a result, many manufacturers have lost the organic capability to rework modern PCB’s, especially those that incorporate BGA’s, opting to hire outside contractors to perform more difficult repairs. This paper will examine advanced tools and techniques that incorporate infrared (IR) or radiant heating technologies to perform non-destructive, highly reliable and high quality rework on complex area array-laden assemblies. Topics that will be discussed include: advantages and disadvantages of infrared versus convective heating; use of nozzles in BGA/area array rework; optimal IR wavelengths; survey of the most advantageous types of IR emitters; the critical role of bottom-side preheat; simplified thermal profile development; non-destructive thermocouple techniques and the proper use of a non-contact, closed-loop IR pyrometer to maintain the target profile; and advanced rework application tips when using IR technology.

Highly reliable and high-yield prototyping in the early stages of development is crucial for innovations in next generation microelectronic systems to demonstrate the results of research. This prototyping is typically based on the combination of Flip Chip technology, SMD assembly, and sometimes wire bonding; all are used to build a functional system from heterogeneous components.

Prototyping typically consists of low manufacturing volume, with batch sizes ranging from 1 to 50. The stages of prototyping include: pathfinder run, first test, system optimization (including component optimization and layout changes), and manufacture of full batches. To achieve this level of flexibility, tool-less manufacturing is mandatory. For the application of solder paste, solder jetting is ideal for prototyping as no stencil is necessary and paste deposition designs can be quickly modified.

A research project was set up to correlate jetting and soldering quality to monitor changing properties over solder paste lifetime. Solder paste jetting behavior, deposition geometry, tackiness for component placement, and solderability/wettability are properties that define the process quality throughout assembly. The impact of solder paste aging and environmental conditions of jetting and soldering quality was studied using optical profilometry and electrochemical impedance spectroscopy (EIS). An optical profilometer was used to qualify the solder paste after jetting and soldering a defined array of deposits. EIS was used to monitor changes in the solder paste prior to and during its jetting application. This paper will demonstrate how in-depth analysis of solder paste is essential to ensure high-yield processes and high-quality prototyping.

Different types of components with soldered bottom terminations are increasingly used in the electronics industry with the principal objective to improve heat dissipation.

The large areas of the solder terminals are an advantage for the heat to escape. However, if the thermal pad design is not optimal or the assembly process not properly adjusted, big voids could be created in these solder joints. The industry criterion for acceptable voiding for thermal pads wettable area is <50% for class 1, 2 and 3 [1]. But there is no established limit for unacceptable voiding, anything above 50% is treated as a “process indicator” for Class 2 and 3.

As heat dissipation improves with less voiding and single large voids may create hot spots, it is important to achieve as low voiding amount as possible and prevent large voids from forming.

There are many parameters that affect the amount of solder joint voiding. Optimization of the stencil design together with a good choice of solder paste, or solder preforms, and a good assembly process have the potential to significantly lower the thermal pad solder joint voiding and to increase the soldered area.

X-ray images of two typical Quad Flat No-lead (QFN) thermal pad solder joints generated from different solder pastes, but otherwise identical process setup, are shown in Figure 1 (shown in paper).

The actual design of the thermal pads is also important. In this presented study, different thermal pad designs to minimize voiding and maximize soldered surfaces for QFN thermal pad solder joints have been investigated.

The purpose was to find thermal pad designs for standard QFN packages that result in consistent solder joint voiding, well below the acceptable limit [1], and have as large soldered surface area as possible.

The Semi-Additive Process (SAP) is a standard process to enable very fine lines and spaces to produce highly sophisticated Integrated Circuit Substrates (ICS). When operating with lines and spaces (L/S) of less than 10/10 µm, the copper thickness variation is one of the critical parameters; it must be controlled within a tight range to avoid reliability problems in assembly or during the lifetime, as described in several papers [1, 2]. Also, new packaging technologies—like 2.1D and 2.3D—are requiring L/S in the rage of 2-5 µm for the Redistribution Layer (RDL), as shown in the examples in Figures 1 and 2 (shown in paper).

These new 2.1D or 2.3D packaging technologies do have much higher requirements on the electroplated copper than the ones deposited with the electrolytes used for PCB or standard IC substrates, with L/S of less than 15 µm. The new copper plating electrolytes and processes need to be able to fill the technology gap between current semiconductor technology and the current IC-substrate technology, as shown in the Figure 3 (shown in paper).

The challenges and requirements for such a new copper electrolyte to fill the gap between the organic IC substrate and the semiconductor technology are increasing more and more with the shrinkage of the L/S and the smaller pattern features on the substrate. The following characteristics of a new copper electrolyte are getting very important:

1. Excellent shape of lines/tracks

2. Blind Microvia (BMV) filling with low dimple

3. A very good within-panel distribution (WPD) of the plated copper

4. Surface appearance of the electroplated copper with low surface roughness

5. Excellent copper-crystal structure, ductility, and tensile strength to enable a good reliability

6. Possibility to plate at a high-current density to operate under low manufacturing cost

7. Cyclic Voltammetry Stripping (CVS) controlled dosing of electrolytes

8. Particle-controlled electrolytes (manufactured under cleanroom environments)

9. Controlled purity of the electrolytes (trace metal controlled)

Therefore, the continuity of innovation and invention as expected by Moore’s Law is needed also on the copper electrolyte side to reduce cost and increase capability to cope with the latest packaging technologies like 2.1D or 2.3D. Challenges like within-panel distribution become a critical factor for the subsequent processing steps.

This technical paper will contain results of copper thickness and the copper thickness variation also called within-panel distribution (WPD), microsection pictures, design of experiments (DOE) results, BMV filling performance, ductility results, and copper crystal structures of the new developed electrolyte. Finally, the chemistry has been further enhanced by producing it under semiconductor standards using high-purity chemicals and ultrafine filtration, tracing all by-products to have the utmost control of the copper plating chemistry. Such a new copper electrolyte was developed to cope with these challenges. All the characteristics mentioned above have been tested with the new electrolyte formulation. Because of the success of this new formulation, it is already used in more than 15 production lines worldwide..

The next generation devices using high frequency of 5G to mmWave and greater has called for innovation in materials used in electronics manufacturing to realize the optimum signal integrity and performance. The selection of materials is critical especially at the printed circuit board (PCB) level for minimized insertion loss. The right choice of surface finishes is paramount for signal integrity and overall reliability of electronic assemblies.

The novel surface finish with nano-engineered barrier layer-finished with an outermost gold layer has shown superior benefits in 5G-mmWave frequency PCB technologies. The technical evaluation of signal integrity at 5G-high band, mmWave and higher frequencies with novel surface finish comparing with alternatives will be discussed. Furthermore, reliability evaluation will be highlighted involving novel surface finish.

PCB Fabricators have long since abandoned Hot-Air Levelling, with several alternative final finishes (ImAg, ImSn, OSP, ENIG and ENEPIG) now well established as having a track record of meeting fabricators cost/performance requirements. As system designers continue to respond to new performance demands, it can be noted that ENIG/ENEPIG finishes have endured as a leading choice in many advanced applications where reliability is prioritized over cost.

Electroless nickel (EN) deposits have served well as a barrier layer preventing copper migration to the outer gold or palladium-gold surfaces, enabling the robust solderability performance of ENIG and ENEPIG finishes. However, with the recent introduction of the 5G mobile network creating growing demand for smart phones, networking, and wireless connections, all requiring increased “data flow”, the need to reduce the signal loss at higher frequency bandwidth is becoming vitally important. The low conductivity and magnetic properties of EN affect electrical signals as they travel along the conductor’s outer surfaces leading to insertion losses at higher frequencies.

As a result, fabricators are once again looking to newer generation surface finishes to meet their performance criteria. EPIG and Silver-Gold (AgAu), as well as reducing the EN thickness from traditional ENEPIG, have all gained some attention in recent times. This paper will review and compare the performance attributes of the leading candidates for a high frequency alternative surface finish