IPC-TR-587 technical report, ‘Conformal Coating Material and Application ‘‘State of the Industry’’ Assessment’ [1] outlines an IPC study of major conformal coating types, coating application techniques, and coating cure technologies, characterizing the final film thickness on common component surfaces. In many cases, the film thickness, although visually not zero, was below the limit of measurement. In ‘Conformal Coatings: State of the Industry Vs of state of the Art’ [2] it was clearly demonstrated that conformal coating coverage and thickness are clear performance indicators of the propensity for a coating material to provide protection in harsh environments, e.g. condensing, salt-spray, immersion and mixed flowing gas etc.

Whilst state of the art materials improved protective performance by at least two orders of magnitude compared to the legacy materials, the paper highlighted areas for improvement, especially with regards to component tolerances. A natural, slight shift in position of components during soldering could yield very different coating patterns and coating coverage, resulting in inconsistent protection from one board to the next.

In this paper, we show how the creative use of liquid coating chemistry can permanently solve coverage issues within the current application paradigm, leading to improved ruggedization performance outcomes in immersion and condensing environments. The results clearly show consistently improved results for the new approaches providing significant enhancement of ruggedization performance.

Contamination of electronic assemblies can occur at any process steps and can be of different natures such as oxides, organic residues, or dusts. Those contaminations could reduce the reliability of PCBA through time. At the same time, miniaturization and new component typologies require ever-higher performances with ever-increasing functionality. Moreover, the industry is looking for solutions to improve cleaning efficiency, reduce costs and limit environmental impact. Thus, developing cleaning solutions become a challenge to guarantee the reliability of the electronics assemblies.

This paper introduces a new technology of cleaning solution developed to be compatible in several processes. After a short description of co-solvent and aqueous process, the cleaning results concerning the new technology that can work in both processes are shared. The cleaning efficiency is evaluated using IPC standards: visual inspection under microscope, ionic contamination, and SIR test. Surface tension is also measured.

Then, a scoring method based on the GHS labelling system and REACH regulation is used to evaluate the environmental impact of this innovative cleaning solution technology.

As a conclusion, the new cleaning solution does show promising results. For aqueous processes, this improvement allows to lower the cleaning time and/or the cleaning temperature. For co-solvent processes, the cleaning performance is similar with an improvement of the safety and the environmental footprint.

As new materials have been developed over the last few years, including the increasing use of thinner dielectrics and spread glass to help improve electrical performance, new issues have been introduced into the fabrication process.

Some of the issues with these new materials include increasing thickness variation due to low pressure areas and uneven copper distribution through the stack, and voiding due to lower resin flow. More complex designs can include thin drilled and plated subassemblies requiring hole fill, which can be a challenge for the fabricator due to scaling or stretching of the materials during the planarization process. This issue becomes even more exaggerated with softer RF materials.

This study looks at solutions to these problems and includes via filling without the planarization step. We also look at methods to produce very flat surfaces to enable more accurate back drilling and produce a flatness tolerance acceptable for large ball grid array packages during the assembly process. Spread weave glass materials have limitations due to low resin flow through the glass and can cause voiding. This limits the designer and can force the addition of more layers using lower copper weights for power planes. Micro cracking is caused by resin rich and resin poor areas having mismatched CTE values. The heavy weight of the copper is a challenge to produce without some level of voiding. This study looked at a 20-layer 4oz copper planar magnetic design in which a high flowing non-reinforced material is employed to overcome these challenges.

In recent years, most research on high-density interconnect (HDI) PCBs focused on microvias. Based on previous test results in the frame of the ongoing research project on HDI PCBs for space applications, it is believed that even stacked microvias do not reduce the reliability of the HDI PCB if designed carefully, manufactured properly and assembly is performed with caution. Under these circumstances, based on extensive testing with various test methods, the buried or core via remains the first HDI structure to fail during reliability testing. The following contributing factors to buried via reliability are discussed: design parameters such as via pitch, drill diameter, aspect ratio, material choice and presence of non-functional pads in combination with manufacturing variables such as plated copper thickness inside the buried via and the use of plugging paste. Test parameters for various test methods such as chamber thermal cycling, interconnection stress testing or air-to-air thermal shock can highlight the impact of these contributing factors. Observations from several test campaigns are corroborated with finite element method (FEM) modeling to better understand the respective failure mechanisms.

This paper presents some of the recent in-situ studies of drop impact reliability for electronic equipment using Finite Element Analyses. The work covers simulation methods, verification with test data, and failure modes.

Three major aspects triggered this investigation.

First is the design optimization of new electronic equipment for automotive industry. The new era of electrification with new design concepts, new electronic components, and the requirement to survive accidental free falls leads to the need for a robust and predictive method. As of today, Finite Element Analyses is an attractive method to build virtual samples, loading scenarios and design variants to fulfill quality requirements, be competitive, and be ready to market.

Second is the missing reproducibility of drop tests. The simulation and test results reveal the stress level and failures at the interconnect are substantially scattered in case of free-fall testing. A guided drop may not perfectly reflect the reality, but is the only way to remove randomness from the experiment, which is prerequisite to science-based problem solving.

Third are the failure modes that are seen around a Ball Grid Array (BGA) package. The newer resilient solder alloys with more creep may show no damage after a drop test but transfer the impact stress to the Printed Board (PB). This can lead to a failure between pad and board, known as pad cratering. The difficulty consists in finding a material limit for testing and simulation to predict this failure mode.

Reliability testing applying surface insulation resistance (SIR) measurements to materials that are used for electronic devices is a fundamental task in the automotive industry. SIR measurements based on the B52 test board (IPC-9202) was further developed with a derivation of a mathematical tool allowing the prediction of ECM failures on the ppm level. The underlying equations are based on SIR measurements that were carried out under step-load conditions for different material combinations on B52-PCBAs. It could be shown that the SIR level and its scattering in repetitive measurements is a clear indicator for the ECM risk, depending on the local humidity. The set of equations based on design of experiment (DoE) evaluations were set up in a way so that a risk factor can be calculated as a function of design, applied voltage, local humidity, and applied assembly materials of the PCBA. In combination with statistical methods, this mathematical model allows, in a practical way, to predict the risk of ECM failures. It can calculate expected ppm failure rates from humidity load collectives which can be obtained from operational conditions of electronic control units in the field. The approach thus represents a new module in reliability engineering of humidity-induced defects.

Server hardware is often interconnected with high-speed, insulated copper cables to transfer data several meters or more between other servers, network hardware, and storage devices within datacenters. Over the last few decades, data transmission speeds have increased significantly. As speeds have increased, the dielectric properties of electrically insulating cable jacket materials have become increasingly important to ensure adequate and reliable signal integrity for long-distance, high speed data transmission.

This paper details the failure analysis investigation of 40 Gb/s high-speed data transmission cables that began experiencing signal integrity issues four years after being manufactured. Failing cables were experienced high insertion loss (attenuation), which ultimately led to data packet loss and affiliated errors generated by the servers in which the cables were installed. Physical analyses were performed to determine root cause of the failures, including electrical testing, microscopy, Fourier-transform infrared spectroscopy, thermal analysis, aging studies, and rheology. These combined assessments proved that the failures resulted from degradation (reduction of molecular weight and oxidation) of the linear low-density polyethylene (LLDPE) wire insulation. During operation within the datacenters, the LLDPE wire insulation began to oxidize over time, causing an increase in its polarity and related dielectric loss properties. The increase in dielectric loss prompted a corresponding signal integrity degradation of the interconnected cabling paths and resulted in data packet loss during signal transmission. The overall insulation degradation was traced to an uncontrolled manufacturing process at the wire manufacturer. The failure analysis methodology and experimental results are presented in this paper.

The surface mount technology (SMT) process is well known and mostly measured in terms of efficiency, cycle time (CT) and first time quality (FTQ). Once the Customer’s needs are fulfilled (demand needs covered and FTQ meeting expectations), most companies feel comfortable enough to do the regular key process indicator (KPI) monitoring, guaranteeing the process is under control. Nevertheless, we must start to look deeper to find the “hidden losses”, so we can extract as much performance as possible from the process. The main goal of the SMT process is to add value by placing surface mount devices (SMDs) as fast as possible and with zero defects. To do so, it is a must to have the right technology and optimized placement machines, according the product specifications.

A certain SMT process might have a great OEE, higher than 85% and single digit ppm FTQ, but still not be fully using all installed capacity. If the total placement installed capacity is 150000 chips per hour (cph) and it is being used to place 100000 cph, it means a 30% loss of potential capacity. The components per hour metric (CPH metric) is poor in this example and leads to the “hidden losses”. Keep in mind that efficiency is still 85%, FTQ at single digit and customer demand are being met.

This paper will focus on the requirements needed to implement a central database for printer recipes and minimize setup time required to begin production. The SMT process works best the more we minimize the human intervention required. With electronic manufactures embracing the concepts of Factory 4.0, it has become clear that recipe control has become a vital element to maintain a stable and repeatable process. Removing recipes that are machine-based and implementing a central database has shown to improve overall quality and job-to-job repeatability. This capability has been available on equipment for years and the advantages known; however, the issue has been setup time from when the recipe is loaded until the product is running at acceptable results for both alignment and print results. This machine-to-machine variation has stifled the implementation and is often the cause of failure. The following paper will outline the steps to implement a central database recipe process and how to synchronize the individual machines to minimize setup and time to production.

SMT and electronics manufacturing industry experts are unanimously moving forward to have line controlling and automation in their digital transformation journey. Typical A typical SMT line formation consists of Solder Paste Printing (SPP), Solder Paste Inspection (SPI), Pick and Place machine (PnP), reflow oven, and Automated Optical Inspection (AOI).

Now, SMT manufacturers see the bigger picture on top of single automation solutions, such as better SPI yield or better AOI quality gate control checks. The new focus is to look at the entire line operation, utilizing digital solutions to eliminate pain points and address long-term operational strategic visions.

Line controller will act as a collaborative agent to orchestrate line processes, which consist of man, machine, material, and method (4M) elements. Line controllers intend to reduce complexity by coordinating and consolidating disparity in the line to enable machine-to-machine (M2M) communication for better productivity and quality control. Practical use cases:

• Multiple lines orchestration - Enable planning/dispatch teams to identify the most compatible line with the least effort for the next changeover run, where manual approach may take at least 1-2 hours for data review and to get the optimum line to perform conversion.

• Central monitoring and controlling - Improve mean time to resolution (MTTR) of the line. Without such an approach, operators need to be on standby at each SPI, PNP, and AOI stations.

• Integrate machine, recipes, and material information - Optimize material stock planning to enable just-enough materials to start the line and just-in-time material replenishment. In high mix productions, material preparation into consideration with 4-6% material buffer to reduce possible logistic time loss between production and warehouse.

• Smart changeover - Auto recipe download for the next lot recipe in queue and informs operators to perform the changeover.

• Flexi line formation - Configure new machines into a single orchestration platform (line controller) instead of multiple, siloed applications.

• PCB eMap interchange – Detailed PCB data collection and avoid unnecessary material consumption. With assumption of 98% yield from SPP, it is possible to save 2% of unnecessary material consumption at the PnP.