The surface insulation resistance (SIR) of conformal coatings was investigated using increased stress by high voltage bias up to 1000V. Test boards had been prepared according to IPC-9202, using components withstanding high reverse bias voltage. Pads arranged in comb structures had been added to assess different creepage distances according to IEC 60664-3 and IPC 2221B.

The electrochemical performance was tested by a SIR test at different bias voltage levels from 500V to 1000V, at static humidity condition of 65°C/93% relative humidity (RH), for a duration of 1000h. The sequence was followed by a damp heat test under the same bias condition, according to IEC 60068-2-38 without frost phase. The effects of the increased voltage stress on the surface insulation resistance were investigated according to the creepage distance and the withstand voltage level of the components.

A positive influence of conformal coating protection on the electrochemical reliability under higher voltage bias was shown. Conformal coatings show a potential to reduce creepage distances under the protected areas, if the material combinations of printed circuit board (PCB) materials, soldering process, and conformal coatings are compatible.

This procedure can be a basis of electrochemical reliability testing of PCB assemblies for elevated voltage requirements.

Polymeric conformal coatings are used to improve and extend the reliability of printed circuit boards against environmental conditions. There is high interest in using light-curable conformal coatings due to their process benefits over conventional technologies, including the ability to use a non-solvated 100% solids material, higher throughput, space savings, and lower operating costs. Light and moisture dual-curable conformal coatings were developed to ensure the curing of the coating even if the material flows underneath components on circuit boards. The use of light-curing coatings in aerospace and defense applications has been limited due to stringent low ionic content (MIL-STD 883 method 5011.7) and low outgassing (ASTM E595) requirements. A recently developed technology enabled formulation of a coating that meets these requirements without giving up the process benefits of the light and moisture dual cure conformal coatings. In this paper, the ionic content, outgassing, and reliability testing, such as, heat and humidity (85oC, 85% relative humidity), sequential thermal shock and cycling (-65oC to +150oC), and salt spray corrosion resistance will be discussed. These results are compared against “out-of-kind” conventional conformal coatings used in the aerospace and defense industry and an “in-kind” light and moisture curable conformal coating.

In the latest IC substrate PCBs, via holes have downsized and these diameters have minimized below 10μm, which have led to the issues of connection reliability. In a conventional process, adhesion failures have occurred between inner copper layer and plated copper films in via holes because the direction of copper crystals changes and nanovoids exist at the interface of electroless copper plating. To align the direction of crystallized copper in via holes, the thinning of electroless copper plating is effective; however, the reduction of thickness can cause a low covering power and the increase of the resistance values in the conventional process.

Concerning the process newly studied, we succeeded to solve the problem of the covering power by controlling the growth of electroless copper plating at via surface and via bottom respectively, and to inhibit a rise of the resistance values by increasing copper purity. The observation by backscattered electron images in field emission scanning electron microscope verified that the crystallized copper aligned toward the same direction at via bottom in the new process. From the results by solder heat resistance test, no adhesion failures were found and improving via connection reliability was proved in the new process. This work demonstrates that the new process can make the thinning of electroless copper plating possible and can align the direction of the crystallized copper between the inner copper layers and the plated films; consequently, the improvement of via connection reliability is achieved by thinning electroless copper plating.

IPC J-STD-004B standard prescribes general requirements for the classification and testing of soldering flux for high qualify interconnections. This standard defines the classification of soldering materials through specifications of test methods and inspection criteria. The materials include liquid flux, paste flux, solder paste flux, solder preform flux, and flux-cored solder.

This research will use the proposed IPC-53 Surface Insulation Resistance (SIR) test patterns by means of an open comb (2D) and closed comb (3D to simulate a component over the comb pattern). The 2D open comb has uniformity of conductor spacing, sheet resistance, and flux outgassing. The 3D-closed comb simulates the effect of leadless or bottom-terminated components, which have non-uniform sheet resistance and flux outgassing.

The response variables will include SIR testing and visual imaging. The objective is to investigate IPC test method improvements for characterizing soldering fluxes using leadless components with narrow pad-to-pad spacing.

Crimped electrical contact reliability is controlled through strict manufacturing processes and verifications, including pull force testing. Cable and wire harness assemblies’ standards provide the minimum pull force for reliable cables. However, in practice, failures occur at a much higher tensile strength than the minimum required.

The first section of this paper reviewed 780 pull force tests provided by NASA that were analyzed to determine how the data compare to NASA’s pre-existing requirements from cable/harness standards. The measured tensile strength of most of the contact/conductor pairs exceeded the minimum pull force values of NASA-STD-8739.4 and IPC/WHMA-A-620 by at least 100 %. The contact/conductor pair samples’ tensile strength followed a normal distribution with an average tensile strength that was at least 182 % of the minimum requirement, and all samples analyzed passed pull force testing. In addition, the 95 % confidence interval of the average tensile strength distributions for several contact/conductor pairs was plotted as error bars to show that the contact/conductor pairs will meet and surpass the requirements.

The frequency of pull force testing can be problematic for projects because of the cost and availability of spare contacts for the destructive test. It is possible to reduce the frequency of pull force testing if at the beginning of the production run, the conditions of the crimp tool and materials are verified, and the settings of the tool remain unchanged throughout the process. However, the project needs to evaluate the impact to risk from reducing the frequency of testing prior to implementing process changes.

Today’s electronics industry is grappling with increasing demand for more customized products, shorter development cycles, supply chain disruptions, and tighter margins. In the PCB manufacturing market, SMBs now predominate; lifecycle processes are often siloed and handled by geographically disparate teams. Having already established that Design for Manufacture (DFM) and Supply Chain confirmation are vital and valuable components in the product lifecycle, we propose that the next logical step is bringing collaborative analysis capabilities to the cloud to create a digital twin of the PCB lifecycle and align all stakeholders with a common goal.

This paper reviews market trends for adoption of cloud-based tools, correlated from independent research and publicly available sources. Real-world case studies are used to examine how cloud-based DFM and collaboration is changing the playing field by enabling egalitarian access to information that affects planning, influences decisions and reduces time-to-market.

The soldering of THT components through solder waves is a thermal process. However, current design rules, guidelines and guideline catalogs do not map the soldering heat requirement of a solder joint. Therefore, this approach cannot ensure sufficient solder fill according to IPC-A610 at the design stage. This requires objective models for evaluating the design data concerning manufacturability. These models have considerable potential, both technologically and economically. In addition to automated manufacturability checks, the automatic and model-based determination of optimized soldering programs results in potential reduction of scrap, shorter process development and more robust processes. Extensive studies of experimental, numerical and analytical models for the prediction of minimum solder fill are the basis for successful artificial intelligence (AI)-based modeling of THT-selective wave soldering. On this basis, it is possible to train meaningful AI models and actually validate the solder fill. The mentioned approaches will be highlighted in this paper and it will be shown how they can be profitably applied in practice from electronics design to manufacturing.

An In-containing mid-temperature solder paste (MTS) has been developed and successfully used in mobile phone board-stack soldering with a 200°C peak temperature profile [1]. It is now being tested for a wafer-level package (WLP256) application using reflow profiles with peak temperatures ranging from 200°C (P200) to 240°C (P240). SAC305 was used as the control, which was reflowed using a traditional lead-free soldering profile (P240). With the constant paste-to-ball volume ratio of 1:4, the joint morphology changed with the reflow profiles. Under the 200°C peak reflow, hybrid joints were formed, in which the mixing zone, dominated by the MTS, was present at the PCB side while the area above the mixing zone maintained the original SAC305 morphology. Inside the mixing zone, In was present in the form of a InSn4 (γ) phase, Sn(In) solid solution, and likely, In4Ag9 particles. Increasing the reflow peak temperature to 210°C (P210) and above, the homogeneous joint was formed, which indicated the fully-merged SAC305 ball with the MTS paste during reflow. The homogeneous joint morphology was similar to the traditional morphology of SAC305, in which an Sn dendrite was surrounded by a Ag3Sn precipitate network. In most likely existed in In4Ag9 participles and the Sn(In) solid solution. The temperature cycling test (TCT) was conducted with a -40/125°C and 20-minute dwelling profile. Regardless of the reflow profiles, the MTS outperformed SAC305 in TCT. The P210 profile forming the homogeneous joint, resulted in the best TCT performance, which was more than a 30% improvement than its counterpart using SAC305 paste. The other profiles also improved the characteristic life at least 11% more. Using the same reflow profiles, the MTS had also demonstrated that the drop shock performance (g-force >6000g) was at least comparable to or significantly better than SAC305, in which the P220 (220°C peak temperature) reflow, forming the homogeneous joint with the paste-to-ball volume ratio of 1:2, led to the best drop shock performance—more than 90% enhancement than SAC305. Although the reflow profiles impacted the performance, the failure modes remained similar to SAC305.

There has been increased interest in reducing energy consumption during SMT assembly over the past few years. Increasingly, the environmental, financial, and regulatory effects have been demanding new innovations. Low-temperature solder alloys have also been of increased interest to the SMT industry for a variety of reasons including component sensitivity, step soldering, and reduced energy consumption. However, while the reduced temperature and subsequent energy during reflow have often been listed as a benefit, it has rarely been publicly quantified. In this paper, we quantify the effect of reduced temperature on oven energy usage by recording the actual consumption rate of an oven under different reflow conditions. The demonstrated reduction in oven energy consumption may then be used by manufacturers to evaluate tradeoffs and benefits of low-temperature solders.

In the last few years there have been concerns in the industry especially in the products requiring high reliability when using microvia structures. As a result many fabricators have been mandating push back on complex high layer count designs which has resulted in very conservative rules for designers to use and meet the fabricators capabilities. Some fabricators have also struggled to ensure even simple structures are built reliably and with repeatability. This study was to look at materials which would ensure that more complex structures could be built reliably. Traditional thin fiberglass reinforced dielectric layers can have issues with the lack of resin movement through spread glass necessitating higher resin to glass ratios for the manufacture of stacked microvias. Current industry practice has been to limit designs to staggered vias or to 1-2 layers of stacked microvias. This work extending a previous study presented at Apex 2022 1 will show how a thin hydrocarbon dielectric layer can be used and optimized for stacked microvias that demonstrates solid thermal reliability up to 5 levels of HDI. It also shows there seems to be no indication yet of a ceiling on how many layers could be used and introduces buried vias and how they affect the reliability for offset versus direct attach of via structures.