Direct Digital Manufacturing (DDM) is a growing field in which Additively Manufactured Electronics (AMEs) are manufactured on a single machine through a variety of additive and subtractive techniques. The maturation of this technology has seen increasingly ruggedized, conformal, multilayer circuit structures that have received interest from defense and aerospace sectors. While AMEs have been successfully applied in rugged terrestrial applications, the technology is ready to advance into an even more severe environment. Presented in this work are DDM advancements to enable the additive manufacture of low-earth orbit (LEO) small satellites.
LEO conditions and general satellite operation require new manufacturing and design methodologies in DDM. Mechanical development towards novel Fused Deposition Modeling (FDM) techniques ensured the printed satellite structure could survive LEO temperature ranges and launch stresses. Resulting structures are strong while maintaining dense electrical and thermal functionality. Higher voltages, long range communication, and the need for efficient power handling drove development of new conductive deposition and component securement methods. Resulting circuitry saw increased density, efficient operation, and feature numbers that far exceed typical additive electronics. The additively manufactured nature of the satellite requires a unique and flexible satellite design which blends printed electronics with commercial-off-the-shelf (COTS) devices. These developments have culminated in a modular small satellite system, in which electrical functions are embedded within the printed structure of the satellite, and can be manufactured on a single DDM system. The volumetric savings and manufacturing agility of this satellite highlight the powerful application of DDM for electrically functional structures.

Thorough cleaning processes are necessary due to their critical role in ensuring optimal system performance. Residual contaminants can significantly compromise printed circuit card assemblies' reliability and operational life. Specifically, contaminants soluble in water and possessing ionic properties can exacerbate issues when exposed to moisture, causing undesirable dendritic growth, corrosion, and, ultimately, system failure.
Advancements in board designs have increased heat generation within electronic systems, necessitating more efficient cooling methods. Immersion coolants are highly effective agents for dissipating the generated heat, and most immersion coolants exhibit limited or no miscibility with water and possess limited capability to dissolve various forms of ionic contaminants. This characteristic has sparked discussions on whether traditional cleaning processes are warranted for systems utilizing immersion-cooling mechanisms.
To address this question, test vehicles were subjected to surface insulation resistance testing while immersed in commercially available immersion-cooling fluids to evaluate long-term reliability. Critical parameters such as the level of cleanliness, exposure to moisture pre-immersion, type of coolant, and the type of flux are systematically analyzed and discussed. The goal is to understand how these variables could potentially influence the reliability of products in the context of immersion-cooled assemblies, providing insights to address whether traditional cleaning processes are still needed.

Additive Manufacturing (AM) offers numerous benefits over traditional manufacturing methods, such as realization of unique form factors, decreased waste in material, decreased cost and lead time of tools, and the ability to create rapid prototypes. It is for these reasons that there has been a significant increase in its use in different technical applications, including electronic packaging. In previous studies, AM techniques have been used to create Poly-Ether-Ether-Ketone (PEEK) Near Chip-Scale Interposers (NCSIs) into BGA PCBs manufactured via traditional methods. The conformal vertical interconnects were made using Aerosol Jet Printing (AJP) in five-axis configurations, and the interconnects that connected the interposer to the BGA leads were printed using syringe-dispense methods. This work expands on the prior research by using the optimized parameters and design of experiments to implement AM interposers into a dual-channel, X-band MMIC assembly.

At millimeter-wave frequencies, considerations of electrical performance and PCB durability may often lead to contradictory requirements with respect to copper foil materials and chemical pre-bond treatments. For example, decreased surface roughness will typically decrease conductor loss but may compromise PCB durability. These issues are being investigated by the iNEMI consortium performing a rigorous study, based on copper foils from different manufacturers, where surface roughness and loss properties of the foils are independently evaluated. An original contribution from the authors of this paper resides in providing easy-to-use instruments, based on mmWave resonator heads, for measuring the effective conductivity of copper foil samples. Such techniques alleviate the need for manufacturing a test vehicle (such as a strip-line segment) and naturally deliver the loss due to the copper, separated from any substrate losses, as no substrate is involved in the measurement.
This paper and conference talk will explain the physical fundamentals of the developed methods, illustrated with the results of copper foil measurements in the 13- 40 GHz range.
We shall focus on Sapphire Dielectric Resonators (SaDR) and plano-concave Fabry-Perot Open Resonator (pc-FPOR), developed with the use of full-wave electromagnetic modeling. Conformal FDTD method is applied for both instrument design and physical insights into the measurement process. Extensions to higher frequencies are underway and will be signaled.
The presented testing methods will help copper foil manufacturers improve manufactured products quality and accelerate new product development. New and better foils will contribute to advancements in PCB manufacturing and overall 5G technologies.

As the electronics industry continually strives for innovation and efficiency in assembly and rework processes, the exploration of low temperature (LT) solder alloys has gained significant attention. This paper provides a comprehensive analysis of LT solder, particularly focusing on its application in rework processes and the broader implications for electronics manufacturing. We delve into various facets of LT solder, examining both the potential benefits and the challenges associated with its use.
The study revisits previous work on LT solder in rework, offering a detailed summary and suggesting a cautious approach due to the increased costs and complexities associated with bismuth-containing solder wire, alongside a lack of substantial differences in joint strength and reliability compared to traditional methods. Additionally, the paper addresses broader considerations of LT solder, including benefits and drawbacks, performance tradeoffs, and areas for further study.
This investigation into LT solder is further enriched by new data on the cleaning of bismuth oxide residues and the effects of tip temperature and contact time on IMC formation during rework. By providing a thorough overview of existing research and new findings, this paper aims to offer valuable insights to manufacturers, engineers, and researchers, contributing to informed decisions regarding the adoption and integration of LT solder in electronics rework and assembly.

The global interest in reducing CO2, as demonstrated by carbon neutrality, is growing in order to achieve a low-carbon society. Electronic packaging industry is seeing the importance of SnBi-based low-temperature solder (LTS) as it can reduce CO2 emissions during the assembly process.
While the soldering temperature of conventional SnAgCu solder is approximately 250℃, the temperature of SnBi-based low-temperature solder is approximately 170℃, enabling processing temperatures as low as 80℃. Despite the possibility of low-temperature assembly, SnBi-based low-temperature solder poses specific challenges and its use in the market has been limited.
The issues with SnBi-based low-temperature solder include the reliability of solder joints and the non-coalescence of BGA balls and solder paste known as HiP (Head-in-Pillow). Furthermore, in recent years, there has been an increased focus on electrical reliability, including electromigration, which is not exclusive to SnBi-based low-temperature solder.
This study presents the research results on the aforementioned phenomena from the perspective of SnBi-based low-temperature solder.

Solder paste jetting is a popular and innovative method for applying solder paste in electronic assembly, especially for modern, miniaturized, and complex electronic assemblies. This technique provides several advantages over traditional solder paste printing methods. Compared to solder paste printing, solder paste jetting allows for precise control over the volume of paste deposited, as well as capability to print on various materials like flexible substrates, within cavities, and on top of previously placed components easily, without the need for custom made step stencils. Moreover, solder paste jetting minimizes the need for movement on z-axis there by enhancing the deposition speed. In addition, jetting improves the ability to deposit solder paste onto surfaces of varying heights.
Due to the inherent customization of depositions with jetting solder pastes, these materials are often used in conjunction with stencil-printable solder pastes in the same process line. Successful integration of jetting and stencil printable solder pastes in the same assembly line requires careful attention to formulation compatibility. Any formulation changes which will alter the characteristics of the two solder pastes in question, especially with respect to reflow and cleaning, can either result in added process costs or yield failures.
In this paper, the cleaning compatibility of jetting and compatible printing solder pastes will be analyzed. The paper will first outline the solder pastes selected for the cleaning compatibility study. Four pastes were selected in total: one no-clean stencil-printable paste, one no-clean jettable paste, one water-soluble stencil-printable paste, and one water-soluble jettable paste. The paper will then outline the different cleaning chemistries that were tested on these four pastes, all four pastes tested individually. The paper will discuss the process for assembling and cleaning the test boards, as well as the visual inspection performed for each component after shearing, according to IPC standards. Finally, the paper will discuss the results of the visual inspection, ion chromatography, and surface insulation resistance (SIR) testing to determine the best cleaning chemistry scenarios for each of the pastes in question.

Continuous pursuits for higher data rate, larger network capacity, lower latency communication, and better energy efficiency have motivated the rapid development of high-frequency communication technologies in recent years. Owing to the skin effect, the alternating electric current (AC) tends to distribute to the outer of a conductor in high-frequency transmission, such that the surface roughness of interconnects becomes an indispensable factor of the signal transmission characteristics. The focus of this study was to quantitatively investigate the effect of Cu-foil roughness on the signal transmission characteristics at mmWave frequency bands. The signal loss on differential striplines with different Cu-foil roughness was simulated by the Groisse and Huray models through using a 3D electromagnetic simulation software (HFSS). Furthermore, experimental measurements were conducted by using a vector network analyzer (VNA) to characterize the signal characteristics arising from different surface roughness, so as to validate the numerical simulation results. This quantitative analysis not only advanced our own fundamental knowledge in surface modification of the high-frequency materials but is greatly beneficial to the development of the 5G communication technologies. Detailed analyses on the high-frequency signal transmission performance of the differential striplines made of different Cu foils will be presented in this paper.
Keywords: 5G, HFSS, Roughness effect, Cu foil, Huray model, Groisse model.

Laser depaneling is a relatively clean separation process but nevertheless the knowledge of potential influence factors on the technical cleanliness is of central importance to find the optimal layout for demanding applications. Especially in industry sectors such as automotive and medical technology, technical cleanliness is one of the key requirements to ensure a reliable and secure function of the PCB and consequently the product. This paper presents an in-depth analysis of the particle contamination for different laser variants, cutting strategies and panel designs. Therefore, the panels have been processed with a tab and full cut as well as with the target for maximum performance and maximum cleanliness of the cutting edge on three different laser systems. In addition, design changes have covered different material thicknesses of the panel. The particle examinations comprise a particle extraction and subsequent analyses with optical light analysis as well as optical particle counting. The results of the measurements are verified against standards for technical cleanliness in the automotive (VDA19.1/ISO 16232) and medical industry (USP 788). This paper is examining in how far these fundamental standards can be achieved for all observed laser variants, designs and cutting strategies by identifying the largest metallic and non-metallic particles as well as counting and grouping the particles regarding their size. In addition, the authors are investigating the correlation of those variable factors and their impact on the level of technical cleanliness, allowing recommendations for the design of printed circuit boards to be derived from it.

The multilayer PCB is prone to poor expansion and shrinkage due to the influence of high temperature and high pressure during lamination process, which may cause risk of abnormal quality. The traditional method is to estimate the compensation value manually, which has low efficiency and great influence of human factors. The quantitative relationship between the compensation value and the expansion and shrinkage value is also unclear. In this context, this article establishes the base material expansion and shrinkage control index system, and uses descriptive statistics, correlation analysis, scatter plot and trend line analysis to carry out qualitative and quantitative analysis on the influencing factors and compensation ratio of expansion and shrinkage for different layers PCB, so as to effectively control bad expansion and shrinkage to improve production efficiency.