Cleanliness level of PCBs is becoming more and more critical given component miniaturization,component density,and manufacturing practices that include no-clean solder flux. The reliability of high risk circuitry (Class 3-Class 1) assemblies requires clean assemblies with field protection using a conformal coating; including poly-para-xylene vapor deposited films. Residues from the manufacturing process limit the level of adhesion of conformal coating on a PCB. Conventional liquid coatings are limited in their uniformity under,around,and across the component,given the application method. The adhesion on hard to reach areas –one can argue-is not a major concern with liquid coatings,but an argument can be made for leadless components where the power and ground are in close proximity. Poly-para-xylene coating is truly a conformal coating that has the potential to penetrate crevices,bottom side of components,board surfaces,component surfaces and cavities present on the component. The purpose of this paper is to research the value of cleaning under Bottom Terminated Components before Conformal Coating. A QFN surface insulation resistance test vehicle,with sensors placed under the component termination will be used for this research. The designed experiment will study both cleaning and non-cleaning before poly-para-xylene coating. The response variables will be measured: 1.) Visual Inspection of Post Soldering Residues,2.) Site Specific Ion Chromatography and 3.) Surface Insulation Resistance using the IPC TM650 2.6.3.7 test method.

PCB design has evolved greatly in recent years becoming ever more complex. Board density is increasing,component standoff heights are decreasing and long term reliability requirements are greater than ever,particularly for Class III products. Given the quality and reliability demands for complex PCBs,manufacturing processes are qualified; that is,the PCB design,including component and solder paste/flux selection,material compatibility and process steps,must meet the long term reliability requirements demanded and quality standards desired. As a result,cleaning is becoming a mandatory step within the manufacturing process. Analytical tests are key elements to any qualification process. Through the IPC,numerous tests have been developed and have been added to industry standards. In particular,IPC-TM-650,method 2.6.3.7 or SIR (Surface Insulation Resistance) is frequently used regardless of the solder paste/flux type. Per the specification,this test can quantify the deleterious effects of fabrication,process or handling residues on SIR in the presence of moisture. Measuring changes in surface resistance is a standard way of testing cleanliness and long-term reliability of a test board or complete process assembly based on industry standards. There are numerous test vehicle options available to the industry for conducting SIR analysis. This study was designed to compare different SIR test vehicles,from a cleaning perspective,in order to determine which,test vehicle is tougher to clean and therefore challenge the cleaning process. The three (3) test vehicles selected were the IPC-B-52,IPC-B-36 and the SMTA Saber. Each test vehicle was populated with specific components. The authors chose to reflow the test vehicles with water soluble solder paste only,since the high activity flux in the water soluble paste would increase the chance of SIR failure if left partially cleaned. Multiple test vehicles were prepared. Cleanliness verification and validation was completed by visual inspection underneath all components as well as by performing SIR tests. All test vehicles were cleaned prior to reflow and ion chromatography was conducted on selected test vehicles initially to ensure they were free of any ionics. An inline cleaning process was used for all cleaning trials.

PCB board manufacturers engage in a number of wet processes. Water is used ubiquitously in many of these processes for rinsing as well as bath make-up. The impacts of water quality on production processes and product quality are many times ignored. Cleaning surfaces to achieve defined levels of cleanliness in terms of particle and other contamination is now a topic of new ISO standards. Many PCB sites do not use high quality water due to the assumption of high costs. This paper discusses how high purity DI water can be produced at lower costs using a DI recycling approach using a technology called EDI (electrodeionization –which is an electro-membrane technology),in PCB production. A discussion of this new technology that allows lower costs of DI production and recycling will be presented. This paper will also present customer and various third party data on how high purity water reduces contamination build up on parts,during processing,improving product quality and reducing rejects.

The High Density Packaging (HDP) User Group has completed a project evaluating the high frequency loss impacts of a variety of imaged core surface treatments (bond enhancement treatments,including chemical bonding and newer low etch alternative oxides) applied just prior to press lamination. Initial high frequency Dk/Df electrical test results did not show a strong correlation with any of the methods utilized within this project to measured surface roughness. The more significant factor affecting the measured loss is the choice of pre-lamination surface treatment. Most of the new chemical treatment systems outperform the older existing systems which depend upon surface roughness techniques to promote adhesion.

Development of information and the telecommunications network has been outstanding in recent years,and it is required for the related equipment such as communication base stations,servers and routers,to process huge amounts of data in short periods of time. As an electrical signal becomes faster and faster,how to prevent signal delay by transmission loss is a big issue for Printed Circuit Boards (PCB) loaded on such equipment. There are two main factors as the cause of transmission loss; dielectric loss and conductor loss. To decrease the dielectric loss,materials having low dielectric constant and low loss tangent have been developed. On the other hand,reducing the surface roughness of the copper foil itself to be used or minimizing the surface roughness by modifying the surface treatment process of the conductor patterns before lamination is considered to be effective in order to decrease the conductor loss. However,there is a possibility that reduction in the surface roughness of the conductor patterns will lead to the decrease in adhesion of conductor patterns to dielectric resin and result in the deterioration of reliability of PCB itself. In this paper,we will show the evaluation results of adhesion performance and electrical properties using certain types of dielectric material for high frequency PCB,several types of copper foil and several surface treatment processes of the conductor patterns. Moreover,we will indicate a technique from the aspect of surface treatment process in order to ensure reliability and,at the same time,to prevent signal delay at the signal frequency over 20 GHz.

The High Density Packaging (HDP) user group working on high frequency test methods,used for speeds above 2.0 GHz,is developing a way of comparing how sensitive each of the various high frequency test methods are in measuring the effect of moisture content on a laminate material’s dielectric constant and loss. In the completed Phase 1 of this work [1],higher moisture content appeared to cause as much as a 20 percent increase in loss with some test methods. The Phase 2 project work was needed to a develop an effective method of determining the moisture content in high frequency test coupons. Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized in this work.

Due to the arrayed nature of the Computed Tomography (CT) Detector,high density area array interconnect solutions are critical to the functionality of the CT detector module. Specifically,the detector module sensor element,hereby known as the Multi-chip module (MCM),has a 544 position BGA area array pattern that requires precise test stimulation. A novel pogo-pin block array and corresponding motorized test socket has been designed to stimulate the MCM and acquire full functional test data. The pogo-pin block design has specific features which capture and guide the pogo-pins while still allowing for easy pin replacement at the test vendor. In addition,the socket design includes many unique design elements,including built-in protection for the pogo-block from user access,thermal control considerations,and stop features to prevent over clamping. Additional mechanical design features to blind-engage a flexible circuit with the MCM will be discussed. The entire socket and pogo-block system is replicated to create a multi-socket tester that is currently deployed at the OEM vendor. This test system enables full characterization of the MCM including gain connectivity testing and full linearity testing of the device. Various additional aspects of the test system will be discussed,including software control of the socket and data collection of the entire signal chain. This type of test socket architecture can be a model industry example for in-circuit test as well as for final functional testing of a BGA type device.

Automated Optical Inspection (AOI) is advantageous in that it enables defects to be detected early in the manufacturing process,reducing the Cost of Repair as the AOI systems identify the specific components that are failing removing the need for any additional test troubleshooting. Because of this,more Electronic Contract Manufacturing Services (EMS) companies are implementing AOI in to their SMT lines to minimize repair costs and maintain good process and product quality,especially for new component types. This project focuses on the testing of component package 03015 which is challenging for AOI. Highly-automated and effective test methods are becoming a more and more important topic in our industry today. Advances in modern manufacturing technologies have been making factories smarter,safer,and also more environmentally sustainable. Finding and implementing smart machines which provide real time information is critical to success. Currently we have been successful in using 2D/3D AOI for production; however not for the upcoming 03015 components. Therefore,we are working with AOI vendors to ensure successful testing of this component type,with a special emphasis on optimizing algorithm threshold settings to detect defects. We have been working with five AOI vendors with 5 test vehicles (PCBAs). Each PCBA board has 246 components with three different pitch sizes (100µm,150µm,200µm). The results of Attribute GR&R,Defect escapes,and False Call PPM (parts per million) will be presented. Based on the data which we received up to now,every set of data (5 sets – still waiting for results of AOI system 3) is from the algorithms of 2D AOI although some machines have the3D AOI capability. These machines have shown different levels of performance. AOI system 5’s results have an excellent acceptable level for Attribute GR&R; both AOI system 5 and AOI system 6 have only several percentage points of a Defect Escape rate. However,this study is just in its infancy; more improvement and testing will be performed. We will continue to provide new test results from all suppliers.

The industry continues to face the challenges associated with BGA,QFN/BTC,and LED packages. The demand for more performance by consumers drives change,which results in greater component density. Component density on printed circuit boards continues to decrease with a corresponding increase in component complexity and reduction in pitches. Good examples of these industrial trends are smartphones,tablets and wearables. In modern production lines,the complexity of these devices drives manufacturers to rely on automated equipment and strict production processes to control variables such as paste deposition volumes,reflow times,and component placement when working with new boards. However,in a rework scenario,controlling all of the variables required to remove and replace one component is challenging. Each of the variables involved with soldering these devices require management on an individual basis. Herein lies the challenge. Many rework processes are still manual ranging from hot air pencils to automated rework machines. These tools are required to duplicate the production process on an individual level. Solder balls up to one thousand I/O and a pitch of 0.35mm on a BGA are becoming more common than 0.4mm or 0.5mm in a package size of 14mm square. QFNs,traditionally,are difficult to rework due to their excellent thermal characteristics. QFNs with a0.35mm pitch and double row terminals on the perimeter and various size ground pads in the middle are increasingly common. LED technology has seen a massive growth,with larger packages and higher wattage output in today’s leading edge printed circuit boards. Higher wattage output requires the use of metal backplanes to dissipate the heat. Contrast the backplane requirement with a relatively low temperature lens and the challenges become evident. This requires more thermal energy in rework without melting the case of the LED. This is a different situation to when LEDs first became mainstream. This paper will show rework processes for all of these challenging components.

The electronics industry has widely adopted Sn-3.0Ag-0.5Cu solder alloys for lead-free reflow soldering applications and tin-copper based alloys for wave soldering applications. In automated soldering or rework operations,users may work with Sn-Ag-Cu or Sn-Cu based alloys. One of the challenges with these types of lead-free alloys for automated / hand soldering operations,is that the life of the soldering iron tips will shorten drastically using lead-free solders with an increased cost of soldering iron tool maintenance/ tip replacement. Development was done on a new lead-free low silver solder rework alloy (Sn-0.3Ag-0.7Cu-0.04Co) in comparison with a number of alternative lead-free alloys including Sn-0.3Ag-0.7Cu,Sn-0.7Cuand Sn-3.0Ag-0.5Cu and tin-lead Sn40Pb solder in soldering evaluations. Tests included solder alloy spread tests on copper,brass and nickel substrates. Soldering iron tip tests done with low silver cobalt containing alloy showed reduced erosion as compared toSn-3.0Ag-0.5Cu solder alloy. The cobalt in the lead-free solder wire was found to create barrier layers between the iron in the soldering tip and the solder,reducing solder tip erosion by as much as 50%.In addition,Sn-3.0Ag-0.5Cu surface mount soldered component test boards were reworked at the soldered chip component locations with Sn-0.3Ag-0.7Cu-0.04Coand Sn3Ag0.5Cu wire to simulate rework in manufacturing operations. Assessment also included pull tests of the soldered lead-frame component joints. The results of the tests are reported.