Soldering is the bonding of metallic surfaces via an intermetallic compound (IMC). The interaction between thermal energy delivery,flux chemistry,and solder chemistry creates the solder bond or joint. Today,reliability relies on visual inspection,operator experience and skill,control of influencers e.g. tip geometry,tip temperature,and collection and analysis of process data. Each factor involved with the formation of the solder joint is an element of risk and can affect either throughput or repeatability. Mitigating this risk in hand soldering requires the identification of these factors and a means to address them. A new technology,which evaluates the quality of the solder joint by calculating the intermetallic compound formation and provides closed loop feedback to the operator,changes the way solder joints are evaluated in hand soldering. Validation of the solder joint requires the ability to identify the correct solder geometry,detect the transition of solder from solid to liquid,and calculate the intermetallic compound formation without adversely impacting throughput or repeatability. Additionally,to be effective,this validation of the solder connection provides real time feedback to the operator and prompts action based on the response. Implementation of this new technology represents a paradigm shift in the hand soldering industry changing the reliance on visual inspection to control of the formation of the intermetallic compound. The validation technology requires two components,software and hardware. The software component is an algorithm that executes the three-step process to calculate the intermetallic compound. The hardware component incorporates a system to store data at the point of use,process the calculations locally and provide feedback to the operator via a visual go/no-go indicator. The validation technology in concert with visual inspection represents a change to the status quo in hand soldering.

The development of novel interconnection materials for production of electronics is of considerable interest to fulfill increasing demands on interconnect reliability in increasingly demanding environments with respect to temperature extremes,mechanical stresses and/or production limitations. Adhesives are playing an increasingly significant role in the continuously evolving electronics industry. Electrically conductive adhesives have developed to the stage that they offer a viable alternative to traditional solders for applications that demand high reliability in structurally challenging environments. Conductive adhesives are often divided into groups based on conductive directions; Isotropic Conductive Adhesives (ICA) normally provide almost equal electrical properties in all spatial directions,and Anisotropic Conductive Adhesives (ACA) which are insulating in an unstressed state,but provide directional electrical conduction through connections between filler particles and the local connection points. Both ICA and ACA have traditionally demanded a high filler content to ensure adequate electrical connectivity. Epoxy based adhesives are often selected due to the vast selection of combinations availability,and traditionally silver fillers are used for obtaining electrical conductivity in ICA. Silver is advantageous since even its oxide maintains high conductivity. Unfortunately,the high cost of silver prevents many applications from using it. An ICA was developed at a much lower cost where solid silver is replaced with metal coated polymer spheres. The polymer spheres are essentially mono disperse in size and can be specifically chosen for different applications. The silver coating of the spheres is approximately 100 nm thick. Specific applications will be presented that highlight the feasibility of the technology with respect to conductivity,structural reliability and lifetime standards. The deposition of the novel ICA has been performed using a jet printing technology to ensure both precise and accurate positioning,size and volume delivery.

With the rapid trend towards miniaturization in surface mount and MEMs lid-attach technology,it is becoming increasingly challenging to dispense solder paste in ultra-fine dot applications such as those involving chip capacitors or BGA packages,as well as dispensing ultra-fine lines in MEMs lid-attach applications. In order to achieve ultra-fine dots and fine line widths while dispensing solder paste,both the solder material and dispensing equipment need to be optimized. Optimizing the equipment can be very challenging,as there are many input variables that can affect the dispense quality of the solder paste. In this paper we will evaluate the many equipment variables involved in the solder paste dispensing process,and the impact these variables have on the dispense quality of the solder paste.

Surface mount components are commonly evaluated for out-of-plane warpage levels across reflow temperatures. Decision making from these measurements is primarily based on signed warpage of a single component surface,per industry standards. However,signed warpage as a gauge can mislead users when surface shapes are complex,or direction of warpage is uncertain. The presented case study analyzes a range of common surface mount components for signed warpage. This wide ranging case study is used to create newly proposed methods for further defining and characterizing surface warpage in a quantitative manner. Analysis of the case study data focuses on two related surface parameters: signed warpage Signal Strength and surface shape naming. Signal Strength is used to classify samples that are in “transition” between positive and negative warpage directions. New methods are shown to represent these transition areas in signed warpage graphs. Surface shape naming is used to further classify surface types,wherein correlation between shape name and surface mount defects are discussed. Algorithms for calculation of Signal Strength and classifying shape names are offered. Real world examples are used to determine appropriate thresholds for sign transitions and shape names in said algorithms. The study proposes a new,industry wide,approach to how companies present component warpage data.

Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard,readily available device packaging methods in which high-density packaging is achieved by: (1) using standard “packaged” memory devices,(2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads,stacked either 2-high or 4-high,and integrated into a single dual-flat-no-lead (DFN) package. To determine thermal cycle reliability,daisy-chain packages were soldered either using lead-free or tin-lead solder with added additional daisy-chain patterns on the PCB to enable resistance monitoring of the stack at thermal cycling intervals. The 3-D stacks were bonded to the board for improving resistance to mechanical loading such as drop and vibration. A number of 2-high and 4-high 3-D stack assemblies were subjected to thermal cycling in the range of -55°Cto +125°C. The daisy-chain resistances were measured at RT and at 50 cycle intervals during thermal cycling. Test results to 500 thermal cycles are presented as well as images gathered from X-ray and optical microscopy to illustrate damage progression and to establish failure mechanisms. Furthermore,comparison was also made between 2D X-ray and X-ray tomography with optical microscopy to determine effectiveness of these non-destructive evaluation techniques. The paper concludes with a summary and recommendations for the next step of investigation.

The multilayer ceramic capacitor (MLCC) has become a widely used electronics component both for surface mount and embedded PCB applications. The MLCC technologies have gone through a number of material and process changes such as the shift from precious metal electrode (PME) configurations which were predominantly silver/palladium to base metal electrodes (BME) dominated by nickel. Each of these changes were accompanied by both quality and reliability problems. The MLCC industry is now in the midst of an unprecedented set of challenges similar to the Moore’s Law challenges being faced by the semiconductor industry. While capacitor failures have historically been responsible for a significant percentage of product field failures (most estimates are ~30%) we are seeing disturbing developments in the low voltage (<250V) commodity part infant mortality and wearout failure rates.

Ionic contamination testing as a process control tool a newly developed testing protocol based on IPC-TM6502.3.25,was established to enable monitoring of ionic contamination within series production. The testing procedure was successfully implemented within the production of high reliability,safety critical electronic circuits,involving multiple production sites around the world. I will be shown in this paper that the test protocol is capable for meeting Six-Sigma-Criteria. For a Gauge R&R study,a calibration solution of 0.1wt.-%NaCl was used in order to investigate the repeatability and reproducibility of the test protocol employing newly developed contamination testing systems,which were placed at five locations worldwide. A total failure range of below 0.1µg/cm²=NaCl at a target value of 1.0µg/cm² = NaCl (±8.8%) was achieved,combined with manual laboratory handling of fluids (pipette,temperature). For process control this value is acceptable and demonstrates that ionic contamination testing based on IPC-TM 650 2.3.25 is able to be used as a process control tool in manufacturing of electronic control units.

There are several industry-accepted methods for determining the reliability of flux residues after assembly. The recommended methods of test sample preparation do not always closely mimic the thermal cycle experienced by an assembly. Therefore,extraction from actual assemblies has become a popular method of process control to assess consistency of post-reflow cleanliness. Every method of post-reflow flux residue characterization will depend on the reflow process followed to prepare the coupon. This investigation will focus on the effect of thermal conditions on the remainder of active ingredients in flux residues after assembly with no-clean solder pastes. Test coupons will be processed using an IR rework station with careful monitoring of thermal profile. In order to characterize the residues,IPC standard SIR testing will be conducted as well as localized extraction,followed by ion chromatography and IC/mass spec for detailed ionic and organic acid analysis. This will essentially characterize electrical reliability,while also quantifying chemical species present in the final assembly and hopefully the relationship between the two. Results will be presented to relate thermal profile to no-clean solder paste flux residues in SnPb and Pb-free processes.

Quad Flat Non-lead (QFN) packages are finding increased uses in high reliability applications due to their smaller footprints,improved thermal and electrical performance [1] and as such there is increased focus on their reliability performance in harsh environments [2 to 5]. In order to investigate issues with condensation and surface insulation resistance (SIR),a range of test vehicles were assembled incorporating QFN components alongside other components,using two advanced production lines in Sweden. These boards were produced with multiple no-clean solder pastes using convection and vapour phase soldering. The aim of the project was to take surface insulation test boards based on the IPC B52 test pattern and assess the impact of conventional SIR testing of QFNs alongside a newly developed condensation test. This condensation test has been driven by an increased requirement to understand the performance of electronic assemblies in humid environments. Whenever there are high levels of ambient humidity,if parts of the assembly drop below the dew point,there is the opportunity for the formation of condensed water on the surface of components and substrate. This can significantly reduce the insulation resistance of the substrate surface,resulting in malfunctioning electronics. Reproducing repeatable levels of condensation during testing can be challenging. Most humidity chambers are designed to achieve stable,well controlled humidity and temperature conditions,but none of these offer condensing options. Therefore the user has to improvise. Existing common approaches include ramping at a fast enough rate to cause condensation,or running chambers very close to 100% relative humidity. A drawback of these approaches is that chambers of different designs will perform differently,and will be sensitive to small drops in cooling performance. At the company,a new approach has been developed where the test board is mounted on a platen whose temperature can be independently controlled without changing the ambient condition in the humidity chamber. Thus,the temperature of the test board can be lowered below ambient to any desired point and hence,produce different levels of condensation. It is therefore straightforward to cycle between condensing and non-condensing conditions on the test board in a constant ambient environment. The technique has been demonstrated to be repeatable and controllable,with the user able to select a temperature differential that matches their worst in-use conditions,or to understand the performance of their system under a range of condensing conditions. Modification of the test board in this project,allowed the group to test the impact of residues under the QFN/LGA packages with the introduction of SIR test patterns under four packages per board. There has been much debate on the reliability of the cleanliness under these packages and the possibility of surface corrosion. This work investigates the current uncertainty. This paper outlines the processes and parameters used for manufacture which featured surface mount reflow and through-hole selective soldering with no-clean fluxes. The results from the same boards with different paste products have been compared with testing under traditional exposure to elevated temperature and relatively humidity plus the controlled introduction of moisture to the test board.

Status of flip chip technology such as wafer bumping,package substrate,flip chip assembly,and underfill will be reviewed in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended. Finally,the competition on flip chip technology will be briefly mentioned.