The oxide layers are known as wetting inhibitors in component and PCB metallizations. The oxide acts as barrier that prevent the tin diffusion from happening. Besides,in corrosion studies,the role of salt residues -with Cl ion-on some metals is known as being promoters of oxidation or corrosion. On the other hand,most of corrosion studies with tin metallization are focused mainly on the corrosion resistance of tin alloys,but little has been done respecting to the influence of salts on tin metallization wetting. In this paper,a series of experiments was carried over to know the influence of specifically NaCl on BGA wetting given Head in Pillow (HiP) as result. The aging of components was done following the procedure of J-STD 002C in which the components are exposed to a low amount of steam water for several hours. As a procedure modification,NaCl was added to the water that forms steam in several concentrations. The results show the more time of steam exposition,the more HiPs are obtained. Additionally,the higher concentration of NaCl in the water,the more HiPs are formed. As a conclusion,NaCl presence could inhibit tin wetting when the proper conditions of energy and environment exist. One interesting fact is during the analysis of BGAs with SEM/EDX; the presence of NaCl was not detected on the solder/BGA ball interface but was found on its edges. This finding would be explained because solder flux tries to remove the contaminants of the interface putting them around the Ball/solder interface. Besides,the oxygen concentration on BGA balls analyzed by SEM increased little or none at all showing the oxide increase cannot be detected by this type of analysis. Because of that,TOF SIMS analysis was carried over showing an increase of oxide on tin surface.

For many years,manufacturing has sought to increase competitiveness by moving off-shore to countries with lower labour costs. Electronic manufacturing services (EMS) companies provided an essential element to make off-shore transfer happen more quickly,offering further cost reduction opportunities from load balancing. Fierce arguments were put forward to protect the loss of local jobs,although the result was,in almost all cases,inevitable. Today,however,the whole market of PCB-based electronics products has changed significantly. The “pros” of off-shoring are no longer what they once were,and the “cons” are becoming more significant because off-shore manufacturing can no longer satisfy the needs of the market. Is reshoring really commercially viable,or are government incentives trying to push water uphill? Market demand patterns continue to change and evolve. As technology-based products become fashionable,the demand from customers becomes more volatile,and they are more heavily influenced by endorsements and trends. Getting the latest products into the market ahead of competitors,with a range of options to match people’s individual tastes,is essential. The trend of direct shipping of products,driven by Internet shopping and direct B2B ordering,brings these variations in demand directly to the factory door. The key for success in today’s market is being able to provide flexibility and agility without losing productivity. Off-shore manufacturing has inescapable issues of delivery time and cost,as well as price depreciation and long response times while carrying some significant risks. Whereas,in theory,reshoring allows rapid time to market,the opportunity to meet customer needs,and eliminates many hidden costs of doing business. In this paper,we expose the real costs of off-shore manufacturing,and put labour cost differentials into perspective. We demonstrate how practically,using existing technologies,re-shored manufacturing can yield better business return,either for an OEM,or through EMS providers.

The old tactic of outsourcing to a low cost geography simply to deliver lowest cost direct and indirect labor was never a panacea supply chain solution. In fact,when evaluating solutions for lower volume and higher mix products typically found in the medical,industrial and public safety segments of the OEM market,IL & DL costs are only one subset of the total cost to land the product and service the ultimate customer. In this paper,there will be examination of what actual cost components should be included in a landed cost analysis,the soft costs that an OEM should consider to deliver outstanding performance in quality,logistics and delivery management of the supply chain solution. A detailed comparison using a “case study” will be presented to demonstrate a total landed cost option versus one that is focused on IL/DL cost. In addition,near-shoring options have developed over recent years initially for consumer oriented products such as cellular phones and printers with the goal of optimization of landed cost in the end use market. There will be shared a few case studies which demonstrate an optimum approach for total landed cost,ease of communication and avoidance of the typical issues that make an outsourcing only approach problematic. These include: different language and culture,long distances and different time zones,investing time and effort on establishing trust and the complexity these elements contribute to the development of long term relationships between an OEM and EMS partner. In summary,Near-shoring,when developed in partnership between the OEM and EMS provider can be a marketing differentiator for those clients who wish to set themselves apart by servicing their customers in the market close to “home”.

The electronic industry is currently very interested in low temperature soldering processes such as using Sn/Bi alloy to improve process yield,eliminate the head-in-pillow effect,and enhance rework yield. However,Sn/Bi alloy is not strong enough to replace lead-free (SAC) and eutectic Sn/Pb alloys in most applications. In order to improve the strength of Sn/Bi solder joints,enhance mechanical performance,and improve reliability properties such as thermal cycling performance of soldered electronic devices,the company has developed a low temperature solder joint encapsulant for Sn/Bi soldering applications. This low temperature solder joint encapsulant can be dipped,dispensed,or printed. After reflow with Sn/Bi solder paste or alloy,solder joint encapsulant encapsulates the solder joint. As a result,the strength of solder joints is enhanced by several times,and thermal cycling performance is significantly improved. All details will be discussed in this paper.

Underfilling is a long-standing process issued from the micro-electronics that can enhance the robustness and the reliability of first or second-level interconnects for a variety of electronic applications. Its usage is currently spreading across the industry fueled by the decreasing reliability margins induced by the miniaturization and interconnect pitch reduction. While material and processing aspects keep pace with the fast technology evolutions,the control of the quality and the integrity of under filled assemblies remains challenging in some cases,especially when considering non-destructive inspection techniques and board-level underfilling. In particular,Scanning Acoustic Microscopy (SAM) which is routinely used for the control of under filled flip-chips turns out to be almost ineffective for usual BGA devices due to the presence of the component PCB substrate. This paper will address the control of surface mount under filled assemblies,focusing on applicable inspection techniques and possible options to overcome their limitations.

The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size,make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition,the low standoff between the die and interposer make it difficult to underfill. A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario,the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate. In this paper,we will discuss various assembly options and the challenges posed by each. In this investigation,we will propose the best method to do 2.5D assembly in an OSAT (Outsourced Assembly and Test) facility.

The world of electronics continues to increase functional densities on products. One of the ways to increase density of a product is to utilize more of the 3 dimensional spaces available. Traditional printed circuit boards utilize the x/y plane and many miniaturization techniques apply to the x/y space savings,such as smaller components,finer pitches,and closer component to component distances. This paper will explore the evolution of 3D assembly techniques,starting from flexible circuit technology,cavity assembly,embedded technology,3 dimensional surface mount assembly,etc. We will explore various technologies available today and some that are starting to appear. This paper will illustrate some of the key items for each technology and what some of the key challenges would apply. The assembly processes needed for each of these areas will be touched upon and what items will be needed to be enhanced for continuing the drive to better utilization of the z axis area available on pcba processing.

No-Fault-Found (NFF) events occur when a system level test,such as built-in test (BIT),indicates a failure but no such failure is found during repair. With more electronics continuously monitored by BIT,it is more likely that an intermittent glitch will trigger a call for a maintenance action resulting in NFF. NFFs are often confused with false alarm (FA),cannot duplicate (CNDs) or retest OK (RTOK) events. NFFs are caused by FAs,CNDs,RTOKs as well as a number of other complications. Attempting to repair NFFs waste precious resources,compromise confidence in the product,create customer dissatisfaction,and the repair quality remains a mystery. The problem is compounded by previous work showing that most failure indications calling for repair action are invalid. NFFs can be caused by real failures or may be a result of false alarms. Understanding the cause of the problem may help us distinguish between units under test (UUTs) that we can repair and those that we cannot. In calculating the true cost of repair we must account for wasted effort in attempting to repair unrepairable UUTs. This paper will shed some light on this trade-off. Finally,we will explore approaches for dealing with the NFF issue in a cost effective manner.

The number one issue identified by the 2009 International Electronics Manufacturing Initiative (iNEMI) Boundary-Scan survey was problems with obtaining correct and compliant boundary-scan description language (.bsdl) files from the semiconductor industry for use in boundary-scan printed circuit board assembly (PCBA) test generation. The major conclusions from the survey were:
•The semiconductor industry needs to make a greater effort to produce correct and compliant BSDLs.
•A better job needs to be done verifying .bsdl file compliance to the implemented JTAG hardware.
Non-compliance is typically found when a test is generated and it doesn’t work! The consequences of not having correct and compliant .bsdl files to generate boundary-scan tests is the inability to generate boundary-scan based tests and if tests cannot be generated,the result is lower overall test coverage for PCBAs which results in higher manufacturing costs and lower overall product quality. The work presented here by the iNEMI Boundary Scan Phase 3: Investigation into Challenges of Using .BSDL Files project group takes a more comprehensive view of the problem by surveying the industry to determine if issues associated with .bsdl files identified in the 2009 iNEMI Boundary-Scan survey still exist (and if so to what extent) and to identify new issues.

As device density continues to maximize the PCB real estate the reflowing of neighboring components or damaging of heat-sensitive components in the rework process continues to cause problems. Devices either have to be removed,thereby reducing rework throughput,or devices get damaged during the reflow process if not shielded from the heat generated during rework. The shielding solutions used most commonly either cannot be delivered in a timely fashion or offer very limited protection to these heat sensitive devices. A new,flexible heat shielding solution is now available that can be easily modified by the users and is inexpensive enough to have on hand. Most importantly it is an effective way to reduce the temperature on nearby components during the reflow/rework process so that neighboring devices do not go into reflow. This study documents the relative effectiveness of this ceramic nonwoven material as well as different shielding materials in protecting neighboring components during PCB rework.