Numerous 3D stack packaging technologies have been implemented by industry for use in microelectronics memory applications. This paper presents a reliability evaluation of a particular package-on-package (PoP) that offers a reduction in overall PCB board area requirements while allowing for increases in functionality. It utilizes standard,readily available device packaging methods in which high-density packaging is achieved by: (1) using standard “packaged” memory devices,(2) using standard 3-dimensional (3-D) interconnect assembly. The stacking approach provides a high level of functional integration in well-established and already functionally tested packages. The stack packages are built from TSOP packages with 48 leads,stacked either 2-high or 4-high,and integrated into a single dual-flat-no-lead (DFN) package. To determine thermal cycle reliability,daisy-chain packages were soldered either using lead-free or tin-lead solder with added additional daisy-chain patterns on the PCB to enable resistance monitoring of the stack at thermal cycling intervals. The 3-D stacks were bonded to the board for improving resistance to mechanical loading such as drop and vibration. A number of 2-high and 4-high 3-D stack assemblies were subjected to thermal cycling in the range of -55°Cto +125°C. The daisy-chain resistances were measured at RT and at 50 cycle intervals during thermal cycling. Test results to 500 thermal cycles are presented as well as images gathered from X-ray and optical microscopy to illustrate damage progression and to establish failure mechanisms. Furthermore,comparison was also made between 2D X-ray and X-ray tomography with optical microscopy to determine effectiveness of these non-destructive evaluation techniques. The paper concludes with a summary and recommendations for the next step of investigation.

The multilayer ceramic capacitor (MLCC) has become a widely used electronics component both for surface mount and embedded PCB applications. The MLCC technologies have gone through a number of material and process changes such as the shift from precious metal electrode (PME) configurations which were predominantly silver/palladium to base metal electrodes (BME) dominated by nickel. Each of these changes were accompanied by both quality and reliability problems. The MLCC industry is now in the midst of an unprecedented set of challenges similar to the Moore’s Law challenges being faced by the semiconductor industry. While capacitor failures have historically been responsible for a significant percentage of product field failures (most estimates are ~30%) we are seeing disturbing developments in the low voltage (<250V) commodity part infant mortality and wearout failure rates.

Ionic contamination testing as a process control tool a newly developed testing protocol based on IPC-TM6502.3.25,was established to enable monitoring of ionic contamination within series production. The testing procedure was successfully implemented within the production of high reliability,safety critical electronic circuits,involving multiple production sites around the world. I will be shown in this paper that the test protocol is capable for meeting Six-Sigma-Criteria. For a Gauge R&R study,a calibration solution of 0.1wt.-%NaCl was used in order to investigate the repeatability and reproducibility of the test protocol employing newly developed contamination testing systems,which were placed at five locations worldwide. A total failure range of below 0.1µg/cm²=NaCl at a target value of 1.0µg/cm² = NaCl (±8.8%) was achieved,combined with manual laboratory handling of fluids (pipette,temperature). For process control this value is acceptable and demonstrates that ionic contamination testing based on IPC-TM 650 2.3.25 is able to be used as a process control tool in manufacturing of electronic control units.

There are several industry-accepted methods for determining the reliability of flux residues after assembly. The recommended methods of test sample preparation do not always closely mimic the thermal cycle experienced by an assembly. Therefore,extraction from actual assemblies has become a popular method of process control to assess consistency of post-reflow cleanliness. Every method of post-reflow flux residue characterization will depend on the reflow process followed to prepare the coupon. This investigation will focus on the effect of thermal conditions on the remainder of active ingredients in flux residues after assembly with no-clean solder pastes. Test coupons will be processed using an IR rework station with careful monitoring of thermal profile. In order to characterize the residues,IPC standard SIR testing will be conducted as well as localized extraction,followed by ion chromatography and IC/mass spec for detailed ionic and organic acid analysis. This will essentially characterize electrical reliability,while also quantifying chemical species present in the final assembly and hopefully the relationship between the two. Results will be presented to relate thermal profile to no-clean solder paste flux residues in SnPb and Pb-free processes.

Quad Flat Non-lead (QFN) packages are finding increased uses in high reliability applications due to their smaller footprints,improved thermal and electrical performance [1] and as such there is increased focus on their reliability performance in harsh environments [2 to 5]. In order to investigate issues with condensation and surface insulation resistance (SIR),a range of test vehicles were assembled incorporating QFN components alongside other components,using two advanced production lines in Sweden. These boards were produced with multiple no-clean solder pastes using convection and vapour phase soldering. The aim of the project was to take surface insulation test boards based on the IPC B52 test pattern and assess the impact of conventional SIR testing of QFNs alongside a newly developed condensation test. This condensation test has been driven by an increased requirement to understand the performance of electronic assemblies in humid environments. Whenever there are high levels of ambient humidity,if parts of the assembly drop below the dew point,there is the opportunity for the formation of condensed water on the surface of components and substrate. This can significantly reduce the insulation resistance of the substrate surface,resulting in malfunctioning electronics. Reproducing repeatable levels of condensation during testing can be challenging. Most humidity chambers are designed to achieve stable,well controlled humidity and temperature conditions,but none of these offer condensing options. Therefore the user has to improvise. Existing common approaches include ramping at a fast enough rate to cause condensation,or running chambers very close to 100% relative humidity. A drawback of these approaches is that chambers of different designs will perform differently,and will be sensitive to small drops in cooling performance. At the company,a new approach has been developed where the test board is mounted on a platen whose temperature can be independently controlled without changing the ambient condition in the humidity chamber. Thus,the temperature of the test board can be lowered below ambient to any desired point and hence,produce different levels of condensation. It is therefore straightforward to cycle between condensing and non-condensing conditions on the test board in a constant ambient environment. The technique has been demonstrated to be repeatable and controllable,with the user able to select a temperature differential that matches their worst in-use conditions,or to understand the performance of their system under a range of condensing conditions. Modification of the test board in this project,allowed the group to test the impact of residues under the QFN/LGA packages with the introduction of SIR test patterns under four packages per board. There has been much debate on the reliability of the cleanliness under these packages and the possibility of surface corrosion. This work investigates the current uncertainty. This paper outlines the processes and parameters used for manufacture which featured surface mount reflow and through-hole selective soldering with no-clean fluxes. The results from the same boards with different paste products have been compared with testing under traditional exposure to elevated temperature and relatively humidity plus the controlled introduction of moisture to the test board.

Status of flip chip technology such as wafer bumping,package substrate,flip chip assembly,and underfill will be reviewed in this study. Emphasis is placed on the latest developments of these areas in the past few years. Their future trends will also be recommended. Finally,the competition on flip chip technology will be briefly mentioned.

Glass offers a number of advantages as a dielectric material,such as a low coefficient of thermal expansion (CTE),high dimensional stability,high thermal conductivity and suitable dielectric constant. These properties make glass an ideal candidate for,among other things,package substrate and high-frequency PCB applications. We report here a novel process for the production of printed circuit boards and integrated circuit packaging using glass as both a dielectric medium and a platform for wiring simultaneously. An ultrafast laser is used to etch away the desired pattern (pads,wires and vias) in the glass,and copper plating is “seeded” through the laser-based deposition of copper droplets. The seeded area is then plated using electroless plating followed by electroplating. Demonstrations of fine pitch wires,variable diameter through holes and blind vias,and a multilayer stack are shown. The deposits have a resistivity less than a factor of 1.5x that of bulk copper for 5-10 mm wires. Plated lines in borosilicate glass of 7-10 µm width and 5-20 µm depth and line spacing down to ~10 µm are demonstrated,as well as vias with a top diameter approaching 100 µm for 150 µm thick glass and 40 µm for 50 µm thick glass. The process presents the potential for significant material savings in terms of base materials,process chemicals,and waste disposal/recycling costs (glass is on the order of 100-foldless expensive than some current high-frequency dielectrics,and wet processes account for a large part of standard PCB/substrate manufacturing). Additionally,the processes are amendable toward other dielectric materials such as FR4,PI,and PTFE-based materials.

Electronics industry has grown immensely over the last few decades owing to the rapid growth of consumer electronics in the modern world. New formulations are essential to fit the needs of manufacturing printed circuit boards and semiconductors. Copper electrolytes for high throwing power applications with high thermal reliability and high throughput are becoming extremely important for manufacturing high aspect ratio circuit boards. Here we discuss innovative DC copper metallization formulations for hoist lines and VCP (Vertical Continues Plating) applications with high thermal reliability and throughput for high aspect ratio PCB manufacturing. The formula has a wide range of operation for current density. Most importantly plating at high current density using this DC high throw acid copper process offers high throughput,excellent thermal reliability,and improved properties for present-day PCB manufacturing. The operating CD range is 10 –30 ASF where microdistribution of = 85 % for AR 8:1 is achievable. This formulation offers bright ductile deposits were plating parameters are optimized for improved micro-distribution and the properties of the plated Cu deposit such as tensile strength and elongation. The Thermal reliability and properties of the deposits were examined at different bath ages. Measured properties are Elongation = 18% and tensile strength = 40,000 psi. All the additives can be easily controlled by CVS (Cyclic Voltammetric Stripping).

Polymer Thick Film (PTF)-based printed electronics (aka Printed Electronics) has improved in durability over the last few decades and is now a proven alternative to copper circuitry in many applications once thought beyond the capability of PTF circuitry. This paper describes peak performance and areas for future improvement. State-of-the-art PTF circuitry performance includes the ability to withstand sharp crease tests,85C/85%RH damp heat 5VDC bias aging (silver migration),auto seat durability cycling,SMT mandrel flexing,and others. The IPC/SGIA subcommittee for Standards Tests development has adopted several ASTM test methods for PTF circuitry and is actively developing needed improvements or additions. These standards are described herein. Advantages of PTF circuitry over copper include: varied conductive material compositions,lower cost and lower environmental impact. Necessary improvements include: robust integration of chip and power,higher conductivity,and fine line multi-layer patterning.

One specific market space of interest to emerging printed electronics is In Mold Label (IML) technology. IML is used in many consumer products and white good applications. When combined with electronics,the In Mold Electronics (IME) adds compelling new product functionality. Many of these products have multi-dimensional features and therefore require thermoforming processes in order to prepare the labels before they are in-molded. While thermoforming is not a novel technique for IML,the addition of printed electronic functional traces is not well documented. There is little or no published work on printed circuit performance and design interactions in the thermoforming process that could inform improved IME product designs. A general full factorial Design of Experiments (DOE) was used to analyze the electrical performance of the conductive silver ink trace/polycarbonate substrate system. Variables of interest include trace width,height of draw,and radii of both top and bottom curvatures in the draw area. Thermoforming tooling inserts were fabricated for eight treatment combinations of these variables. Each sample has one control and two formed strips. Electrical measurements were taken of the printed traces on the polymer sheets pre-and post-forming with a custom fixture to evaluate the effect on resistance. The design parameters found to be significant were draw height and bottom radius,with increased draw and smaller bottom curvature radii both contributing to the circuits’ resistance degradation. Over the ranges evaluated,the top curvature radii had no effect on circuit resistance. Interactions were present,demonstrating that circuit and thermoforming design parameters need to be studied as a system. While significant insight impacting product development was captured further work will be executed to evaluate different ink and substrate material sets,process variables,and their role in IME.