With the adoption of RoHS and implementation of Lead Free solders a major concern is how this will impact reliability. Both commercial and military hardware are impacted by this change even though military hardware is considered exempt from the requirements of RoHS. As the supply chain has moved to the new lead free alloys both markets are being forced to understand these impacts and form risk mitigation strategies to deal with the change. This paper documents the effect of mixing Leaded and Lead Free alloys on BGA devices and how this impacts reliability. Three of the most common pitch BGA packages are included in the study to determine if the risk is the same as pitches decrease. Metallurgical analysis was performed utilizing cross-sections and SEM to study the alloying of tin/lead and tin/silver/copper both separately and combined. MIL-STD-883 Method 1010.8 Temperature Cycling was used to accelerate fatigue life of the samples and testing of those samples was performed at regular intervals using a bed of nails tester. Various reflow soldering temperatures were used to assemble the different combinations of alloys. Under-filling of assembled BGA’s was also studied as a risk mitigation strategy.

Printed & Flexible Electronics
• Development Waves – 1st,2nd,and 3rd
• Essentials
• Products and Applications
• Technology and Infrastructure Development
• Printed & Flexible Electronics Pipeline – Experts Only*

ITO nanoparticles were successfully printed on glass with the AccuPress Gravure System
•A wide range of sheet resistivity values was achieved with different engraving resolutions of the gravure cells.
•A sheet resistivity as low as 415 O/? was achieved through the use of high temperature sintering and 1000 O/? was achieved through the photonic sintering.
•Visible Light transmission above 88% was obtained,regardless of the sintering method of ITO films.

HoP Mitigation is addressed with respect to solder paste,components,inspection,process and the environment.
Graping minimization recommendations are given with data driven suggestions.

Materials Registry for Printed Electronics
- WMU’s CAPE received an award from FlexTech Alliance to create an online database for accessing technical information on functional materials used in manufacture of printed and flexible electronics.
- Purpose:
- Provide increased access to technical information about available products – both research and commercial
- Facilitate greater visibility of material suppliers within the printed and flexible electronics supply chain.
- Strengthen printed electronics industrysupply chain

Manufacturing technology faces challenges with new packages/process when confronting the need for high yields. Identifying product defects associated with the manufacturing process is a critical part of electronics manufacturing. In this project,we focus on how to use AXI to identify BGA Head-in-Pillow (HIP),which is challenging for AXI testing. Our goal is to help us understand the capabilities of current AXI machines.
For the study we used two boards exhibiting HIP defects with four types of AXI machines at four sites in Flextronics manufacturing,or vendor laboratory. The AXI machines used have different X-ray technologies: Laminography and Tomosynthesis. We collected three sets of data with AXI 1 machine (Laminography),and AXI 4 machines (Tomosynthesis); one set of data with AXI2 (Tomosynthesis); and 4 sets data for AXI3 (Tomosynthesis). We studied AXI measurement data with the different AXI Algorithm Threshold settings. The data indicated clearly that the Algorithm Threshold settings are very critical for detecting HIP,including open. The defective HIP pins are validated by using 2DX and CT scan.
The test data consist of Defects Escaped %,False call PPM and also Gage R & R. The AXI images for HIP pins,false call pins and defects escaped pins are presented in the paper. The 2DX and CT images are provided for identifying HIP type (shape and size).

SMT assembly planning and failure analysis of surface mount assembly defects often include component warpage evaluation. Coplanarity values of Integrated Circuit packages have traditionally been used to establish pass/fail limits. As surface mount components become smaller,with denser interconnect arrays,and processes such package-on-package assembly become prevalent,advanced methods using dual surface full-field data become critical for effective Assembly Planning,Quality Assurance,and Failure Analysis. A more complete approach than just measuring the coplanarity of the package is needed. Analyzing the gap between two surfaces that are constantly changing during the reflow thermal cycle is required,to effectively address the challenges of modern SMT assembly.
To fully understand and characterize variation in the gap that is the main cause of solder joint defects such as head-in-pillow,shorts,and opens,analysis of the interface between the mating surfaces needs to be:
• Full-field: A high density of data represents surface warpage much more finely than an approximation such as coplanarity,allowing area-specific review and analysis
• Dual-surface: Making assumptions about how the “bottom” surface is shaped when mounting a component neglects the complex behavior the land area might exhibit during the thermal cycle,and is a deficiency when attempting thorough assembly planning or failure analysis
• Full-profile: Making assumptions about when the single temperature when warpage of surfaces is important during the thermal cycle can lead to missing critical parts of the reflow process,overlooking when defects such as head-in-pillow can be caused
• Statistical: A large enough quantity of samples should be measured to allow confident calculation of expected average,maximum,minimum,and extreme (3s) gaps between surfaces. After measuring warpage of multiple surface mount components and land areas separately,the collected data can be combined into statistical summaries for each temperature point.
Reviewing the combined data at the start of assembly planning can provide an overview of dual-surface warpage at each temperature,and for the entire thermal profile. The measurement and analysis results that follow include a package-to-board assembly interface case study,and calculations,graphs,and methodology highlighting the use of gap limits and pass/fail maps to visualize areas with potential assembly issues.
This analysis method provides new capabilities when planning and monitoring the assembly interface across a full reflow cycle that can help predict and compensate for defects such as head-in-pillow.

The high speed transmission applications in the electronic product become inevitable developing trend. The signal integrity becomes the most important issue in the electronic industry. The material suppliers,PCB manufactures,OEM designer commonly face the serious issue “how to keep signal integrity operated in the high speed transmission” for the modern electronic application nowadays.

The material suppliers dedicated into developing lower dielectric constant and dissipation factor material,PCB manufactures define the low loss material and copper foil selection guide and more delicate process handling. The OEM specify the signal integrity form the insertion loss and extracted material Dk / Df from signal loss result . All of these are for keeping signal could be transmitted completely at higher bandwidth. We discuss the following factors affect insertion loss result in this paper,such as material Dk / Df,copper foil type,skin effect,impedance variation,line width,line space,black / brown oxide treatment,dielectric thickness,via stub effect and so on through TDR and VNA measurement and simulation analysis result .

We hope we could more understand the mystery of signal loss issue through these discussions and meet the signal loss specification from the OEM designer.

Throughout a product’s life cycle it may need to be tested various times. New product designs need to be validated during the prototyping phase,manufacturing defects need to be detected and diagnosed during the production phase,and products may need to be tested and/or updated while they are in use at the end customer,while defective units returned from the field need to be retested. This paper discusses different test access methodologies and elaborates on Embedded System Access (ESA) strategies in particular,with examples for its use in practice.

The growing transmission speed and volume of digital content increases the pressure on reduction of overall insertion loss of printed circuit boards permanently.
In today’s circuit boards,it is not only the transmission line itself,but also the via structure that impacts the insertion loss profile. To optimize the via,the stub length needs to be reduced by methods like backdrilling the copper out of the unused portion of the PTH.
In this paper,the influence of remaining stub lengths – varied between a couple of mils and 100mils - on the insertion loss profile is evaluated. As a second variable the size of the antipad is chosen and a two factor,multiple level DOE is performed.
Both,single ended and differential insertion loss is investigated and an ‘analysis of variance’ approach is used to determine the level of influence of the variables stub length and antipad size at various frequencies up to 40GHz.
The frequency of the quarter-wave-length-resonance is correlated to the stub length as well as the increase of the insertion loss well below the resonance point is discussed.
The paper describes the test vehicle,the performed measurements and discusses the electrical performance characteristics of the various test cells. A recommendation for an acceptable stub length is given.