A great deal of work has already been done to determine the equilibrium temperature of a PCB when exposed to a heat source such as the thermal environment of reflow soldering. This study will go beyond an equilibrium condition and explore the temperature-time distribution of the board when a variable temperature heat source is applied to both outer surfaces. For simplicity,the model will be a two-sided board. Obviously,the model board has two material interfaces. An interesting observation is that anywhere within the board,including the material interface,thermal energy must be conserved. There is not a similar requirement for the temperature. Consequently,at the material interfaces we can expect the thermal properties’ of the board to change in a profound manner. A similar situation occurs when a fluid passes through a shock wave. This will be reflected in such board properties as the thermal stresses in the various layers and the resulting warp. This phenomenon also explains and quantifies why a thermal shock can be devastating while a slow temperature rise to the same endpoint may well be tolerated.
The analysis will use a one dimensional,time dependent model i.e. there are two independent variables. This necessitates a partial differential equation to describe the temperature variation within the board. The boundary conditions are the outer temperature of the board,which is the temperature of the heat source on both outer surfaces. The third boundary condition is at the copper epoxy interface where conservation of thermal energy is required.

A joint project between Flextronics Inc. and North Star Imaging Inc. is being conducted to correlate current x-ray imaging and cross-section analysis of BGA voiding with state of the art high resolution CT-Scan imaging. Our primary objective is to validate the void measurements obtained from non-destructive imaging techniques,with the physically measured void measurements of cross sectioning. A secondary goal is to characterize void properties before and after reflow.
Typical AXI inspection equipment provides one to three horizontal planes of reference for BGA void measurements. CT Scan imaging provides a full 3D volumetric representation of the BGA void,allowing for size,volume,and void position data. Information that can be used in failure analysis and process characterization projects,without physical destruction of the printed circuit board.
Five 50.0 mm FCBGA devices and five 52.5mm FCBGA devices,with known voiding,are being used in the study. The voiding for each device has been measured on a 3D AXI machine (Figure 1),a2D off-axis high resolution x-ray machine (Figure 2),and CT-Scan system (Figure 3). The devices will then be placed and reflowed onto printed circuit boards. After reflow,all the voiding will be measured again using each piece of equipment. In addition,select voids will be cross-sectioned,polished,and measured using a high magnification digital microscope and correlated to the other x-ray imaging tools.

Prior to committing production boards to vapor phase soldering,we performed an evaluation to assess reliability and evaluate the vacuum soldering option. The reliability of vapor phase processed BGA solder joints,with and without vacuum applied,was evaluated by means of a test vehicle circuit board assembly. The test vehicle was designed with daisy chain nets through multiple solder joints. These were designed with all of the solder balls in a chain having a similar distance from neutral point,so this factor could be part of the reliability assessment. The boards were temperature cycled for 8250 cycles of -5 to 95°C,by which time all of the outermost daisy chains had failed. The number of cycles-to-failure was analyzed using Weibull plots and characteristic life was calculated.

Voids in solder joints are representing one of the main problems especially for power electronics. A low and homogeneous
thermal resistance of solder joints is demanded for a quick and uniform conduction of the heat loss from the power chip. The
same applies for the electrical conductivity of solder joints. Enclosed voids can cause a displacement of electrical and
thermal paths and a local concentration of power and heat. In addition,gas voids are anxious to form spheres in the solder
gap,which could be a cause for tilting of chip components and a wedge-shaped solder gap. This is tightening the problem of
patchy distribution of current or heat and is causing stress and cracks.
The amount of voids can be influenced by different measures,e. g. a good wettability of metallization,solder pastes with
special adopted solvents and an adequate preheating profile. However,a special vacuum process step during soldering is
demanded for absolutely void free solder joints. But this vacuum process is associated with some essential disadvantages.
Besides of the technical expenses for vacuum pumps and additional locks,the vacuum process excludes the use of gas
convection for heating and cooling. Apart from a special vapour phase–vacuum technology,most machines are using
infrared radiation or heat conduction for soldering.
The same principles as used in vacuum soldering technology are applicable also for a higher pressure level. If the void in the
solder joint is arising for an excess pressure,the normal atmosphere pressure could be sufficient for escaping of enclosed gas.
Essential for this effect is the pressure difference between inside and outside of solder joint. A benefit of soldering with
excess pressure is the possibility of gas convection for heat transfer. This allows the application of conventional components
and the realization of the usual temperature distribution and profiles.

The world of spring-loaded test probes and special probes for in-circuit and functional tests have grown tremendously over the past few years. Ever increasing demands for electro mobility applications,the telecommunications market and the automotive sector force the manufacturers to think beyond the concepts of a traditional standard probe in order to meet the demands of today’s highly complex test applications. In this paper,we like to demonstrate probing concepts for three different scenarios: (1) High speed probing for fast data rate applications,(2) high current probing for multi-probe-environments and finally (3) pneumatic probing for sequential probing applications and fixtureless installations. The challenge for all application areas but especially for high current and high frequency probes is to not only look at the mechanical properties of a test probe to successfully mate with the counterpart but to follow a holistic approach to combine high frequency behaviour etc. with mechanical aspects.

Test point optimization for the PCB electrical test domain brings the test speed faster for the flying probe tester (FPT),
and the fixture cost lower for the fixture type tester. The importance of optimization is increasing along with the shrink of
PCB design rule,especially for the fixture type testing.
There are 2 types of test point optimization:
1. Probe position optimization (position optimization of the probe contact point in the test pad for the larger
margin). The optimization reduces the probe contact failure for the FPT and fixture,so that the pass rate
increases.
2. Probe type optimization for the fixture type test (selection of optimum probe type such as size and head
shape). In general,the smaller the probe diameter,the higher the probe pin cost. So the cost of fixture
can be reduced by selecting the larger diameter probe pins.

Many companies use “one stop testing” as a solution to the test issues in a manufacturing environment rather than discrete
“islands of test”. Low volume,high mix electronic manufactures are concerned about floor space,which can be expensive.
As well as operator training,which can be considerable if a separate test solution is used for each product manufactured.
Very high volume manufacturers can also benefit from a single stage electrical test solution if the test times are less than the
beat rate of the line. This is especially true if the system in fully automated. As with low volume manufacturers floor space
and operator training costs can be reduced,but the significant saving is in early defect detection that helps reduce scrap rates
and improves line efficiency.
By combining electrical test into one system and having the system directly integrated into the production line,the system
can detect defect at the earliest stage of the board manufacture. As a base,incircuit test (ICT) is a well-established electrical
test technique and has been used successfully for a number of years and has a long history of being integrated into the
production line. PXI has established itself as the standard for cost effective integrating of functional instruments into a test
system. By combining ICT and PXI into one solution,it can perform incircuit test,help overcome ICT access issues and
perform functional tests. This universal test solution provides a smaller footprint,consistent operator interface and overall a
lower cost of test.
This paper will discuss the advantages of a universal integrated electrical test solution,at the normal Incircuit Test stage of
production,to minimize production costs and help improve product quality using two case studies. One is a low volume
high mix manufacturer and the other a high volume automotive electronics manufacturer.

The physical mechanisms behind tin whisker formation in pure tin (Sn) films continue to elude the microelectronics industry. Despite modest advances in whisker mitigation techniques (i.e.,barrier metal underlayers,substrate/film annealing,etc.) and encapsulation,ways to fundamentally prevent whiskers from forming remain unknown. It has been said that tin plating thicknesses of <0.5 um or >20um are “whisker inhibiting”[3,6]. In the case of the former claim,it may be argued that as film grains approach an equiaxed proportion (i.e.,the average columnar grain height is roughly equivalent to the average grain diameter),stress compensation is no longer preferential to the normal direction with respect to the plated film. Grain morphology has often been pointed to in the literature as a likely factor in Sn whisker formation due to the fact that SnPb,which does not whisker,has equiaxed grains while pure Sn exhibits columnar grain growth,which is only equiaxed when the film thickness matches the average grain diameter. Our work examines the effect of adding grain refiners during tin electroplating,with particular focus on the ‘as-deposited’ film morphology and the associated incidence of whiskering. We have included polycrystalline Sn ‘control samples’ in our study,and as an extension of our previous work[1],we have compared the structure and whiskering incidence of nanotexturized Sn on both polycrystalline and nanocrystalline Cu underlayers.

Compliant press-fit zones apply external mechanical stress to copper and tin surfaces of plated through holes at printed circuit boards during and after performing the press-in process. This external pressure increases the tendency to create tin whiskers. These whiskers grow on much shorter time scales than whiskers caused by strain introduced by intermetallic phase growth. Also the length of these whiskers can exceed 2 mm under special circumstances and cause malfunction of electronic circuits. The results shown in this paper support the understanding for the growth mechanisms at different geometrical shapes of press-fit zones and therefore give strong impact on the risk analysis.

Twenty-nine different cells phones have been disassembled,ground up,dissolved and analyzed for elemental content,mainly for information about the metals present in the phones,but also for some metalloids and non-metals. The following elements were detected in some or all of the phones: Be,Mg,Ti,V,Mn,Fe,Co,Ni,Cu,Zn,As,Nb,Ag,Sn,Sb,Ba,Ta,W,Au and Pb. The following elements were not detected: Se,Cd,In,Te,Pt,Tl or Bi. The paper will discuss the method used and propose possible sources in the telephones for certain elements of interest and the reasons for the interest in some of the elements.