With the release of IPC 7093,"Design and Assembly Process Implementation for Bottom Termination SMT Components," earlier this year,the term BTC is the newest acronym to enter the world of SMT. BTCs are very much like the BGAs but without the balls. Excellent electrical and thermal performance combined with lowest package cost has made this package very popular especially in mobile products. However,the absence of balls changes practically all aspects of design and manufacturing SMT assemblies using BTCs. The connection between the package and PCB is essentially like a postage stamp which poses challenges in both design and assembly of BTCs to achieve acceptable reliability. And achieving good yield is also a challenge since both the package and PCB must be perfectly flat. Any warpage in package and PCB has to be compensated by solder paste but too much paste creates voids and package floating and too little paste causes opens and insufficient solder resulting in premature failure. Based on the design and assembly guidelines in IPC 7093 co-chaired by the author,this presentation will focus on key issues in design and assembly to reduce defects and improve reliability.

Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size,such as a near die size footprint,thin profile,and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size,weight,electrical,and thermal properties are important. However,adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow,outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength,ductility,creep,and fatigue life In addition,voids could also produce spot overheating,lessening the reliability of the joints. This is particularly a concern for QFN where the primary function of thermal pads is for heat dissipation. Thermal pad voiding control at QFN assembly is a major challenge due to the large coverage area,large number of thermal via,and low standoff. Both design and process were studied for minimizing and controlling the voiding. Eliminating the thermal via by plugging is most effective in reducing the voiding. For unplugged via situations,a full thermal pad is desired for a low number of via. For a large number of via,a divided thermal pad is preferred due to better venting capability. Placement of a thermal via at the perimeter prevents voiding caused by the via. A wider venting channel has a negligible effect on voiding and reduces joint continuity. For a divided thermal pad,the SMD system is more favorable than the NSMD system,with the latter suffering more voiding due to a thinner solder joint and possibly board outgassing. Performance of a divided thermal pad is dictated by venting accessability,not by the shape. Voiding reduction increases with increasing venting accessability,although the introduction of a channel area compromises the continuity of the solder joint. Reduced solder paste volume causes more voiding. Short profiles and long hot profiles are most promising in reducing the voiding. Voiding behavior of a QFN is similar to typical SMT voiding and increases with pad oxidation and further reflow.

Vern Solberg is an independent consultant specializing in SMT and microelectronics design and manufacturing technology. He has served the industry for more than twenty-five years in areas related to both commercial and aerospace electronic products and is active as an author and educator. Solberg holds several patents for 3D semiconductor packaging innovations and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology a McGraw-Hill publication and furnishes the ‘Designers Notebook’ column for SMT magazine. Vern was also awarded the prestigious ‘Raymond E. Pritchard Hall of Fame Award’ and is currently an active member of IEEE,SMTA,IMAPS and the IPC,the industries standards development organization for electronics. Current IPC activity- Co-Chairman of the task group currently developing the IPC-7092,‘Design and Assembly Process Implementation for
Embedded Components’.

There is no issued industry standard for the workmanship of underfills – either from the perspective of visual examination (a la A-610) or by more intrusive techniques like cross-sectioning. This presentation will highlight what has been put together and submitted to the appropriate IPC standards committee for consideration. Further some challenges faced by trying to meet this standard may be delineated as
well.

The IPC Solder Products Value Council,in cooperation with iNEMI and a group of industry experts,has developed a protocol for testing the physical properties of lead free solder alloys. This presentation will review the status of the protocol’s development,the status of a round robin of the protocol’s test repeatability and then briefly discuss the prospect for developing better reliability models using creep data testing as described in the protocol.

Board-level designers are constantly expected to cram more computational power,into a smaller space,at lower cost,and accomplish this task in less time and with fewer resources. In this rush to meet customer requirements,common and costly hardware design mistakes are often made. Examples include part selection,component placement,board layout and specifications,and understanding the role design plays in ensuring long-term reliability. This presentation provides hardware designers with case studies of some common mistakes and the process by which these mistakes were inserted or overlooked during the design process. The presentation will also provide a checklist to avoid these mistakes,why these mistakes caused failures,and optimized corrective actions necessary to avoid these problems,but still ensure a successful product launch.

Electronic assembly innovations drive more performance using highly dense interconnects. Assembly residues may increase the risk of premature failure or improper functionality. The challenge for OEMs is to quantify safe residue levels and how residues impact long term reliability and functionality of hardware. To compound this problem,the question of “how clean is clean enough” is more challenging as conductors and circuit traces are increasingly narrower.
Highly dense bottom termination components decrease conductor pitch,spacing and standoff heights. The problem is that current spacing trends can yield spacing between printed circuit traces as small as 2 mils. As electrical fields rise,contamination at these narrower traces becomes more problematic due to voltage swings,high frequencies,leakage currents,and high impedance.
The purpose of this research is to build a new test board that provides a more accurate correlation and prediction of assembly residues to one or more aspects of long term reliability. The test board will be populated with a series of bottom termination components and cleaned. The research will follow a three phase strategy:
• Phase 1: PCB layout/Component Library Selection Geometries/Sample Size
• Phase 2 DOE Matrix: PCB Surface Finish,Flux & Cleaning Chemistries,Cleaning Systems/Analysis Techniques using IC,IR,HPLC,GCMS
• Phase 3 Conclusion: DFM approach for PCB designers layout relative to cleanliness limitations to establish a defined PCB design layout to facilitate an acceptable electrical measurement (i.e. fork,divider,capacitance,etc.) via a library of components (i.e.,QFN,PLCC,BGA,etc.) geometries to test cleaner/chemistries capabilities

Printed circuit board (PCB) material properties and surface roughness directly influence attenuation and NEXT/FEXT crosstalk signal integrity of high speed digital interconnect design. Balancing performance,cost,and ease of fabrication requires a quantitative understanding of the impact that the dielectric material and surface roughness will have on the performance of the signal path through gigabit PCBs,backplanes,cable assemblies and connectors. An in-depth understanding of how the material will perform when used to fabricate 25+ layer count boards with thicknesses over 250 mils is required. This paper provides a survey of these problems and of possible measurement solutions,including characterizing signal path integrity,power/ground integrity,materials properties,package/fixture measurement challenges and the surface roughness of copper signal traces.

In this evaluation we will show an ionic residue comparison using Umpire 2 boards that were top and bottom surface mounted with standard reflow and selective wave soldered on the connector and B-24 comb patterns. For this evaluation,30 boards were processed using a no clean flux with lead-based soldering parameters. Three groups were evaluated,Group A (not cleaned),Group B (water only cleaned) and Group C (saponified steam cleaned). The 30 assemblies and 3 unprocessed boards were SIR tested for electrical performance and then each assembly was C3 tested in three locations (0.1 in2 area) and then the entire board was bag extracted.

Counterfeit and substandard parts and components have been a recurring theme in practically every market. For the last several years,the largest concern has been in the military and aerospace industries. Many of these re-marked and recycled parts are coming back into the US from electronic waste that was sent overseas. In an attempt to mitigate risk and potentially eliminate use of counterfeit and substandard parts,it is important to develop a counterfeit inspection procedure for incoming materials. This inspection can be as basic as a visual examination but becomes more successful at identifying potential counterfeit components and parts when a few more techniques that are advanced are employed. This webinar will present background regarding the counterfeit market as well as provide information on various tests and testing techniques for identification of counterfeit parts.