•The 2011 iNEMI Solar PV roadmap
•Involvement of the electronics supply chain
•Example of an electronics opportunity – micro-inverters

• 2010 turned out to be an unexpectedly strong year: > 130% growth in both cell production and installations over 2009
• 24GWp cell production
• All leading suppliers are expanding production capacities at a high rate
• Differentiated,high-efficiency PV cell products are being introduced by all leading suppliers
• CIGS thin-film modules are progressing toward high-volume production,with efficiencies approaching that of c-Si modules
• Thin-film technologies were unable to gain further production share over 2009,due to greater difficulty in expanding manufacturing capacities
• Production is now clearly dominated by Asia,with Europe and Japan continuing to lose importance
• Module price reductions and new incentive programs are leading to greater geographic diversity in installations
• PV installation market is becoming more robust—no longer completely dependent on Germany

Consider defluxing at the design stage. This involves determining how product design may impact the assembly process. It also involves selecting the most effective,rugged defluxing option relative to the assembly design. The reward is reliable,competitive,and profitable electronics assembly. Selecting the right defluxing process must take into consideration not only performance requirements and costs but also miniaturization,component configuration,as well as local,national and international regulatory constraints. Changes in product design and the increase in highly-populated assemblies may impel modification of the defluxing process. Changes in the defluxing chemistry and in the defluxing process can benefit product quality and performance.

Because of the phase out of CFC’s and HCFC’s,standard solder pastes and fluxes evolved from RA and RMA fluxes,to No-Clean,to low residue No-Clean,to very low residue No-Clean. Many companies came out with their cleaning solu-tions,aqueous and semi-aqueous,with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners,two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices.
Past chemicals like CFC’s,HCFC’s,brominated solvents,detergents and glycols cannot do a good cleaning job anymore because most flux formulations have changed. Also,assembly processes have been modified due to smaller components and more compact board assemblies. Thus,it is important to remember that the world is composed of two main things: organics and inorganics. Organics are made of resins and activators,whereas inorganics are made of salts,metallic salts and fillers.
Cleaning performance is affected by three main criteria. The first involves the Hansen Parameters which is a characterization of a contaminant to be dissolved and which can be simplified by the solvency power of a product also known as the Kauri Butanol Index (KB Index). The second is surface tension,expressed in mN/m. This parameter must be considered because when the cleaning product cannot make contact with the contaminants under or around components,the contaminants cannot be dissolved.
This second parameter drives us to the third point,which is physical parameters like temperature,mechanical activities,and the duration of the process.
The mastery to manage all of these parameters while facing high-tech miniaturization and environmental care,like ROHS,REACH,etc. brings innovation to cleaning in this electronic world.

Our insatiable desire for smaller,faster and highly functional electronic devices presents numerous challenges for package designers and manufacturers. Current day popular approaches include stacked components and boards,high I/O density,and short interconnection distances. Unfortunately,these solutions make flux residue removal from underneath components increasingly difficult. Adding to the challenges are the changing global environmental and safety regulations which make the cleaning task even more challenging. The objectives of this study are to 1) evaluate cleaning effectiveness of several currently available cleaning chemistries/processes in removing flux residues from underneath low standoff height components,2) determine differences in the effectiveness of these individual cleaning processes on Sn/Pb and Pb-free solder paste residues,and 3) evaluate inherent advantages or limitations for each type of cleaning chemistry and process.

The process cleaning rate theorem holds that the static rate (chemical forces) plus the dynamic cleaning rate (mechanical forces) equals the process cleaning rate. New lead-free flux residues result from more demanding soldering drivers created by high soldering temperature,surface tension effects,and
miniaturization. Lead-Free flux compositions require thermal stability,resistance against burn-off,oxidation resistance,oxygen barrier capability,low surface tension,high fluxing capacity,slow wetting,low moisture pickup,high hot viscosity,and halogen free. The static cleaning rate for lead-free flux residues is dramatically different from eutectic tin-lead flux residues. To clean lead-free soils,longer wash exposure time,high cleaning agent concentrations,and high levels of mechanical energy are needed. The purpose of this research paper is to measure the cleaning variability induced by lead-free flux residues and to compare the cleanability of lead-free flux residues to determine the viability of new cleaning agent designs.

This paper details the Alcatel-Lucent Pb-free Material Reliability Test board (MRT) used in two different High Density Packaging User Group tests covering 56 different constructions and in numerous other independent material analysis studies [1-7]. In total,this test vehicle has been used in over 80 different material evaluations (and still growing) encompassing materials from almost every major material manufacturer and fabricated by multiple PWB manufacturers. The test vehicle,currently in its 5th generation (MRT-5),is very comprehensive and includes sections for evaluation of material survivability through Pb-free reflow at different via hole pitches,air-to-air thermal cycling,interconnect stress testing (IST) – including the new DELAM methodology introduced by PWB Interconnect Solutions [5,9],conductive anodic filament (CAF) evaluation,moisture sensitivity and its effect on Pb-free reflow survivability,electrical characterization,provides BGA pads for pad pull testing,and incorporates specific design features to enable characterization of material properties (such as DMA) in a multilayer construction in a consistent manner. The design is flexible including 3 different standard constructions and resin contents (12 layer,and 20 layer with 2 different constructions) and can be adapted to other configurations if necessary. This paper presents the design and provides example results and information on how to evaluate these results. The design is made available to all in the industry to facilitate a standard test methodology – and has been offered to IPC as a standard test vehicle for multilayer material evaluations.

The High Density Packaging Users Group Consortium investigated plated through hole reliability of printed wiring board test vehicles constructed with 20 different Pb-free capable printed wiring board materials. The study contained a total of 27 different constructions built by three PWB manufacturers. The materials were tested using both air-to-air thermal cycling and Interconnect Stress Testing (IST) methodologies. The test vehicles combined both via reliability and materials analysis testing capabilities,using two specially designed IST coupons with via to via spacing of both 0.040” (1mm) and 0.032” (0.8mm),All products were constructed with 20 layers,laminated to an average thickness of 0.115” (2.92mm),and drilled with 0.010” (0.254mm) vias,producing an aspect ratio of 11.5 to 1. Seven of the 20 materials were investigated with two different glass styles and resin contents. The materials were IST tested on the two coupons types,both as built and after 6X Pb-free (260°C) reflow. The air-to-air thermal cycling tested a single configuration after 6X Pb-free reflow only. Materials in the test included eight high Tg,filled FR4 materials,six high Tg halogen-free FR4 materials,and six high speed materials. Correlations between the air-to-air thermal cycling results and IST results are detailed,as are the correlations of these results to independently measured and supplier listed material properties.

An important element of the High Density Packaging Users Group (HDPUG) Consortium investigation into the reliability of printed wiring board (PWB) constructed with 20 different Pb-free materials was to understand whether the materials were negatively impacted by the six reflow cycles to 260°C. A new electrical test methodology and associated automated test equipment have been developed to non-destructively measure and compare specific attributes of the PWB’s material construction that identify whether material degradation (delamination) was present. Additional features of the methodology create product construction baselines which confirm that each individual test vehicle was constructed with the same material properties,thickness and glass/resin ratio,all related to changes in dielectric material properties. The data enables the user to estimate the variability of thickness for each dielectric layer within the product construction. The study contained a total of 27 different constructions; built by three high-end Asia based PWB manufacturers. The Interconnect Stress Test (IST) test vehicles were designed to combine attributes to quantify both via reliability and materials analysis testing. Via reliability results and the statistical correlation between IST and air to air oven testing is reported in a separate paper [5]. Using two specifically designed IST coupons with via-to-via spacing of both 0.040” (1mm) and 0.032” (0.8mm),all products were constructed with 20 layers,laminated to an average of 0.115” (2.92mm),drilled with a 0.010” (0.254mm) vias,producing an aspect ratio of 12 to 1. Seven of the 20 materials were manufactured with two different glass styles and resin contents. The materials were tested on the two coupons types,both as built (non-stressed) and after 6X Pb-free (260°C) reflow (stressed). Twenty different material types were tested,which included eight high Tg,filled FR4 materials,six high Tg halogen-free FR4 materials,and six high speed materials. Correlations between the electrical testing and traditional micro sections for the presence of material damage and confirmation of dielectric thickness are detailed.

Accelerated testing of plated hole life is necessary for economic reasons due to the long time to failure during field operating conditions. One difficulty in performing accelerated testing on plated holes is to decide which acceleration model to use. In the work presented here,we will assume an inverse power law relation of cycles to failure versus stress. Stress versus temperature curves will be derived from TMA and DMA data from over twenty lead-free laminates,before and after reflow thermal stress. We will then compare stress versus cycle to failure data for both the lead-free laminates and the two thermal stress conditions,ATC and IST. Completion of this work will enable prediction of plated hole cycles to failure based upon laminate material properties and help to better understand the key role that laminate materials play in plated hole reliability. Also,the two stress conditions will be compared with respect to field life predictions