Examination of historical data for a defunct electronics manufacturing plant in Ontario,Canada has allowed the
determination of the potential global warming contribution by the plant for the years 1971 to 1995,inclusive. The
biggest contributors were determined to be consumed electrical power produced by burning fossil fuels,natural gas
usage,employee travel to and from work and discharge of gaseous chlorofluorocarbons (CFCs),while they were
being used. The latter dwarfed all other contributors.

Solder beading and tombstoning are observed increasingly with chip components as their size decreases. This is
even more crucial in today’s packaging,due to the high ratio of passive components in comparison to active
components. The increasing number of passive components affects the Defects Per Million Opportunities (DPMO),
which inturn affects the overall yield of the assembly line. Hence,it is vital to understand the various causes within
the assembly process,which influence the occurrence of these defects. This paper will discuss the results of a
process characterization study to understand the effects of solder paste,stencil thickness,board support,reflow
profile and the component size on the formation of solder beads and tombstones. A Resolution-V DOE analysis was
performed to determine the effect of these factors on the defect occurrence. The response variable for the study was
% defects,the ratio of number of defect occurrences to the total number of available defect opportunities.

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A new non-halogen flame retardant has been developed and is useful for a variety of high performance applications. This
non-reactive phosphorus-based material satisfies fire safety needs for a broad range of resins including epoxy,polyolefin,and
polyamide. The combination of excellent flame retardant efficiency,high thermal stability and exceptional electrical
properties is unique to this organophosphorus flame retardant and makes it a breakthrough technology for high speed,high
frequency use in fast growing wireless and wired infrastructures. Resin performance data,including formulations with
synergists,are presented in this paper.

Multi-layer organic laminates which make up over 90% of the present types of interconnecting substrates in today’s electronics can develop a loss of insulation resistance between two biased conductors due to a failure mechanism known as conductive filament formation. The probability of CFF is a function of temperature,moisture content,the voltage bias,manufacturing quality and processes,materials and other environmental conditions and physical factors. Filament formation typically appears to arise in two steps: a degradation of the resin/glass fiber bond followed by an electrochemical reaction. Bond degradation provides a path along which electro-deposition may occur due to electrochemical reaction. The path may result from poor glass treatment,from the hydrolysis of the silane glass finish and from mechanical stresses. Microscopic examinations of failure sites have shown that conductive filaments can be formed along de-bonded or delaminated fiber glass/epoxy resin interfaces,due to breaking of the silane bonds. The bi-functional silane molecules act as a link between the glass fiber and resin by forming a chemical bond with the glass surface through a siloxane bridge,whereas its organo-functional group bonds to the polymeric resin. The organosilane bonds are known to chemically degrade by hydrolysis. This paper will characterize the degradation of the interfacial bonds between the glass fibers and organic resin. Analytical technical techniques such as Nano-indentation are used to characterize the quality of the interface and follow the change in this interface as a function of absorbed moisture into the PCB.

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The portable electronics market has driven steep-slope growth for over a decade and continues to deliver amazing handheld electronic devices; manufacturers of these products are facing challenges they thought would be in the distant future: denser electronic substrates,more power demand and more heat to dissipate,stringent use conditions,and more importantly,demand for lower production cost.
Lowering production cost is critical to remaining competitive; hence the objectives become high “first pass quality” and low “returns for failed units.” There is high demand for manufacturing tools and processes that attain these goals.
Conformal coating is a cost effective process used to maintain the functionality of the electronic components inside a mobile device in harsh environmental conditions. This paper discusses recent developments in conformal coating that help enable the manufacturing process to meet the criteria for increased reliability at a lower cost,especially important for high production volume devices that command above average selling price.

The use of plasma processing in the manufacture of electronics is growing as we discover more and more applications for this technology. It is now common for plasma etching and cleaning to be used in multiple stages of the electronics manufacturing process. The introduction of new plasma polymerization methods and equipment has added new possibilities and applications for plasma.
Plasma polymerization is a unique and exciting new tool for our industry. Plasma polymerization is a simple,one step process that can be used to apply a thin,uniform film as a protective coating which requires no curing or the use of any solvents. The chemical structure and properties of the coating can easily be tailored to the requirements of the application by selection of the appropriate precursors and processing conditions. The protective coatings that can be deposited using plasma polymerization represent an opportunity for the industry to deliver new,more reliable products to the market.
This paper will discuss the plasma coating process and the equipment used. The application of this type of coating process to printed circuit boards and electronic assemblies and the results of tests to demonstrate the protection offered by these coatings will also be presented.

The thermal stability of silicone polymers,fluids and resins has been well documented and studied extensively. The high temperature performance of silicone adhesives and sealants used for electronics applications has only moderately been investigated. This report documents the effects of very high temperature exposures to electronics-grade silicone adhesives and sealants for such properties as tensile strength,elongation,tensile modulus,weight loss,shrinkage,durometer,and lap shear adhesion. The goal of the work is to determine application “life expectancies” of the products as well as an extrapolated estimate of the Underwriter’s Laboratories’ “continuous use” temperature rating – the highest temperature at which a product is expected to lose no more than 50% of its original value for whatever key property degrades the fastest
Four different formulations of silicone adhesives and sealants were evaluated for high temperature stability. For these products,elongation was found to be the fastest degrading property among those tested. The data was found to fit a power curve of exposure temperature vs. time to reach a 50% loss of initial tensile strength and elongation to an R-squared value of 0.99 and to a linear fit in an Arrhenius plot to the same very strong fit. These plots could be used to closely estimate the effects ofHeat Aging on the material over a wide range of temperatures.

Circuit complexity and density requirements continue to push PCB fabrication capability limits. Component pitch and routing requirements are continually becoming more aggressive and difficult to achieve in good yield with current fabrication strategies. The trend is to bring the PCB closer to the density requirements currently required for semiconductor packaging. The ability to place interconnecting vias in any location on any layer is crucial to PCB fabricators in meeting this high density interconnect (HDI) trend.
The two fundamental elements in any type of PCB,conductors and dielectrics,both have to be considered when building “any layer” HDI. These PCB’s have specific challenges for processing while maintaining thermal and electrical performance. Careful consideration of the interplay of the fundamental elements is critical to fulfilling all of these requirements.
New methods and materials designed specifically with these challenges in mind are becoming available for building HDI
Using materials specifically designed for HDI PCBs can significantly reduce the challenges producing these boards. However,along with easing the challenges of fabrication,these materials must also demonstrate the right combination of properties to meet electrical and thermal requirements while also being reliable. Validation of these new technologies is currently underway.