The Quad Flat Pack No Leads (QFN) type of leadless package,also known as Land Grid Array (LGA),is rapidly increasing in use for wireless,automotive,telecom and many other areas because of its low cost,low stand-off height and excellent thermal and electrical properties. The implementation of any new package type always results in a learning curve for its use in design and processing,especially for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. In particular,the central termination of these QFN packages are prone,in most practical experience,to exhibit a high,or even excessive,level of voiding when seen under x-ray inspection. Such excessive voiding can not only affect the package?s thermal performance during operation,but it can also increase the stand-off height from the board making the QFN float higher on the solder surface. Such action can apply stresses to the device outer terminations causing them to no longer remain planar and affect joint quality. Therefore,monitoring central termination voiding provides a valuable method to qualify the presence of unsuitable stand-off heights which,in turn,may increase the propensity for open joints during production.
This paper will discuss the results of experiments being undertaken on identical QFN devices where the quantity of solder under the central termination was varied and the ensuing voiding level calculated by x-ray inspection. The results will be discussed in line with correlating this data as a method to provide a suggested upper limit for QFN central termination voiding so as to minimise the possibility of open joints in production.

Stencil printing is a critical first step in surface mount assembly. It is often cited that the solder paste printing operation causes about 50%-80% of the defects found in the assembly of PCBs. Printing is widely recognized as a complex process whose optimal performance depends on the adjustment of a substantial number of parameters. It is not uncommon to hear that stencil printing is more of an art than science. In fact,the process is so complex that sub-optimal print parameters usually end up being used. In addition,stencil printing produces relatively noisy data,which makes the print process extremely difficult to control. Minimizing the variance of the deposited location and volumes will improve the quality of the process and produce more reliable solder joints.
In an effort to improve the performance of stencil printers,continuous process monitoring and statistical process control
techniques have traditionally been used. However,these techniques require constant process tweaking and highly depend on process expertise. Presently,manufacturing engineers tune control parameters to a recommended nominal value suggested by
the equipment and/or solder paste manufacturers. In general,line engineers optimize control parameters by printing a few initial boards and hope that the process stays in control. However,when a process disturbance or drift occurs,the yield of the process typically degrades rapidly to the point of becoming unacceptable.
In general,there are two critical aspects to a printing process. You want to put down the right volume of paste on the right spot. In another word,we not only have to monitor the amount of paste volume we also need to monitor X,Y and ? registration of the board. This issue is compounded when dealing with miniature components such as 0201,01005,0.4 mm and 0.3 mm CSP’s and lead free paste. Lead-free paste is known to have less spread,or wet-ability,and adds to the challenge.
To improve the performance of the solder paste printing process we have identified several control schemes that can be developed into commercial products with no technical risks. These are automated print registration correction,automated stencil inspection coupled with stencil wiping and finally,advanced closed loop control consisting of print parameters adjustment (such as,squeegee speed) based on the 3D SPI volume,area and/or height measurements.
In this paper we present selected results from the first phase of this work focusing on print registration control,using a closed loop control scheme.

Thermo-gravimetric Analysis (TGA) measures weight changes in a material as a function of temperature (or time) under a controlled atmosphere. This technique is currently used in the design phase of lead-free solder paste. In this study,the same technique is used to predict how long solder paste can be left on the stencil before it dries out and is no longer suitable for further use.
In many SMT production lines,the solder paste lies exposed on the stencil for an extended period without being used. This can be due to many reasons: product change-over,machine downtime in the SMT line or just not enough production volume for the line to run continuously. Some chemistry in the paste slowly evaporates even at room temperature. This affects the rheological properties of the solder paste and may result in poor printing,or aperture clogging of the stencil.
Advanced TGA instruments have the ability to simulate a reflow process under different atmospheres. A solder paste can be
heated in nitrogen or air with different gas flow speeds over the sample. The TGA shows that the chemistry of a solder paste
responds differently when the atmospheric conditions change. Knowing this,an optimal heating profile under nitrogen may be different from one when soldering in air. Heating solder paste and determining its characteristics will help reduce the number of solder defects in SMT production.

Since the beginning of Surface Mount Technology over 40 years ago solder paste has been an integral element in electronics assembly. Historically solder paste design and development has been,in a sense,analog in nature. Some users have considered it “black magic”. Formulations were based on previous knowledge bases,honed over the years by tweaking and trial and error science. Paste testing followed suit with virtually all performance tests based on subjective expert inspection and critique. Although statistical design elements have been appending these development methods in recent years,complete digital paste design has been confounded by the lack of quantitative paste tests and the complexity of mixture design technology.
Today we can state that the digital solder paste has been developed by combining “Design for Six Sigma” techniques,quantitative testing methods for all major attributes and specific performance targets derived from a close customer interface. This paper will walk the process of creating this design system,beginning with the building and refining of the “House of Quality” and then coupling this with previously developed quantitative benchmarking techniques,testing and perfecting these techniques for statistical validity,pre-screening potential ingredients,running the mixture Design of Experiments (DOE) and finally verifying the formula. This system has yielded a comprehensive knowledge of interactions for every constituent in the formula,as well as statistically predicted the optimum formula based on desired properties and their relative importance.
There are many obvious benefits to the digital solder paste over its analog predecessors. The design outcome forms a mathematical basis for a chemical formula with the interactive effects on performance attributes for each constituent fully understood. This permits performance simulations of constituent changes,intuitive troubleshooting and other “what if” scenario exercises. Shorter development cycles for formula variations to target key paste attributes are one immediate benefit.

Copper plating is widely used in the electronic industry for fabrication of electronic devices. It is particularly useful for
fabrication of printed circuit boards and semiconductors. Copper is electroplated over the surface of a printed circuit board and onto the walls of the through holes. The mass PCB production requires intensification of and at the same time simplification of the metallization process without sacrificing but instead improving the reliability. Various approaches have been studied in order to plate high aspect ratio (AR) through holes with improved micro-distribution and improved mechanical properties of the plated copper such as Tensile Strength and Elongation. Direct current acid copper PTH (plating through holes) at low current densities as well as PPR plating for high AR (>12) were explored. The parameters of
a new high throw acid copper plating process are described in this paper. The mechanical properties and the thermal characteristics of the plated copper are presented. The results from the throwing power measurements are provided.
A high temperature acid copper process has been also studied. For a large number of PCB fabrication facilities in areas with hotter climates,plating at elevated temperature presents difficulties. Reduced brightness,increased grain size,and increased roughness lead to a decrease in reliability performance. A new process for plating smooth,bright,and planar copper layers at temperatures up to 40C is described. Tensile strength and elongation measurements as well as the thermal characteristics of copper layers deposited at room temperature and at elevated temperatures are given.

The use of electrodeposited copper for filling blind microvias has grown rapidly to become an essential and widely adopted
process used by various Printed Circuit Board (PCB) and package substrate manufacturers. Driven by the need for increased
speed,portability and wiring density,the interconnect pitch on both semiconductor packages and High Density Interconnect
(HDI) substrates continue to shrink. As these designs evolve and dimensions shrink,the ability of copper filling process to
consistently produce void free copper filled microvias comes under increasing pressure.
This paper describes a new pattern-plate,Direct Current (DC) copper electroplating process designed for HDI and packaging
substrate applications. Process performance as a function of processing variables is discussed.

This paper presents a novel electrolytic copper panel plate system incorporating equipment and specially developed electrolyte which enables filling of blind micro vias with a minimum of surface plated copper.
The system utilises Uniplate plating equipment which may be combined into a wet to wet metallisation and copper plating line. The InPulse2 electrolytic copper plating module uses insoluble anodes for uniform plating conditions together with a special clamping system for electrical contact to the substrate which also enables production of material with thin copper foil down to 3 µm. Such material is becoming more common in HDI production but requires special techniques to ensure optimum surface distribution at high production current densities. The insoluble anodes are segmented and each anode segment has an individually controlled rectifier to ensure uniform blind micro via filling over the whole substrate.
Blind micro vias typically seen in hand held devices with 70 µm depth and 100 µm diameter can be easily filled with this system with only 15 µm copper deposited on the surface,this offers the possibility to meet the requirement for 2 MIL line and space with panel plating techniques. Also due to the low thickness of plated copper,savings in materials are very significant particularly in copper metal but also in solder mask and etching chemistry. This process has already reached a high acceptance in the mass production of HDI circuit boards particularly for hand held devices.
Development results showing the system capability also for through hole filling of substrates is shown together with discussion of possible application areas for this new technology.

The plated thru hole has changed considerably in 50 years of electronic packaging,but in its many forms remains the most
common interconnection in 1st and 2nd level electronic packaging,and is still one of the most feared in terms of reliability. The transition from the original solder filled holes to BGA wiring vias,subcomposite buried vias,and today’s microvias has resulted in many new failure mechanisms,not only in the copper interconnections but also in the surrounding laminate,especially with Pb free reflows.
This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing,failure analysis,and other sources. The relative life and failure modes of thru vias,buried vias,and microvias (stacked vs. non-stacked) are compared,along with the affect of structure,materials,and peak temperatures on the above. The origin of via-induced laminate failures such as “eyebrow cracks” and Pb free related internal delamination is also explored. Video clips of laminate coupons during Pb free reflows are shown,including examples of failure mechanisms as they occur,to vividly illustrate the challenges involved and to help reveal the root causes. Finally,an extrapolation to future technology trends for laminate substrates is attempted to address the question—what might be the failure modes of tomorrow,and will via/laminate reliability be better or worse?

European legislation has meant that lead-free solders now dominate mainstream electronics manufacturing. These
replacement solders are all high tin alloys with significantly higher melting points compared to conventional tin-lead materials. Substrate technology has been developed around reinforced resin materials and concerns have been raised regarding the increased degradation caused by the associated higher processing temperatures. This is compounded by the interconnecting structures being brought into closer proximity as a result of increasing technology advances driven by miniaturisation. The removal of non-functional pads to facilitate signal routing and improved drilling conditions for high aspect ratio vias,may also affect substrate reliability.
The National Physical Laboratory and PWB Interconnect Solutions Inc. have undertaken a joint study following identical test structures through both thermal cycling,with constant electrical monitoring (event detecting) and Interconnect Stress Testing (IST). The test vehicles included patterns to monitor changes in interconnection spacing (pitch) and also the effect of removing non-functional pads. The failure modes generated with both techniques were similar as were the relative rankings of the effects. The results showed that the removal of non-functional pads tended to improve reliability for high aspect ratio plated through holes in thicker substrates,although increasing interconnection pitch had little effect on failure rate.
The results generated by both thermal cycling and IST showed extremely good correlation. Failures occurred at a slightly lower number of cycles for IST compared to thermal cycling due to the unique ability of a more stringent failure criterion possible with IST. The relative ranking of the level of failures is identical for both the thermal cycling and IST but the results were obtained in very different timescales. IST has been shown to give a fast comparable result to thermal cycle testing with constant monitoring,but thermal cycling may be more beneficial if a wider range of experimental parameters (E.g. Solder joints) are to be tested simultaneously.

Reliability testing of printed wire boards (PWBs) by thermal cycling offers the ability to compare relative survivability through assembly and reliability in the end use environment. This article delineates an eleven step method to establish a test protocol that will maximize accuracy,applicability and reduced costs and reduce the propensity for confounded data in thermal cycle testing of bare PWBs exposed to lead-free assembly and rework simulation. The method presented in this paper is targeted to the unique challenges afforded by lead-free testing applications and testing of the integrity of conductive interconnections and dielectric materials.