For the last couple of years,the main concerns regarding the electrical performance of blank PCB boards were impedance and ohmic resistance. Just recently,the need to reduce insertion loss came up in discussions with blank board customers.
One approach to alleviate the issue is the change to a lower loss dielectric material. Hence the percentage of boards that require a lower loss material is increasing significantly.
However,changing to a lower loss material influences PCB cost and in addition may affect the reliability of the boards.
The second way to reduce insertion loss is to minimize the conductor roughness. The roughness is influenced by two factors: the initial roughness of the copper foil (as received) and the treatment of the copper surface prior to lamination (a.k.a the oxide replacement).
Our first investigation,presented at Apex 2011,focused mainly on the influence of a wide variety of oxide replacements. The main focus of this follow on investigation is copper foil quality. Several very low profile and ultra low profile copper foils were investigated in a DOE,together with two types of oxide replacements.
The resulting electrical performance characteristics,like impedance,DC line resistance and insertion loss were evaluated in an ANOVA approach.
The paper describes the test vehicle and the testing methodology and discusses in detail the electrical performance characteristics. The influence of the independent variables on the performance characteristics is presented.
Finally the thermal reliability of the boards built applying different copper foils and oxide replacements was investigated.

Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important.
Currently,there is no method for adequately quantifying roughness of a signal trace or a power/reference plane layer within a finished PCB. The measurement methods currently available can only be applied to the base foil,prior to its incorporation into a finished board,as they require direct access to the surface to be measured. In a PCB,this surface is not directly accessible,as it is encapsulated within the board,and attempting to expose the surface will necessarily damage or destroy both the board and the surface of interest.
This paper describes a method by which the surface roughness of a metal foil or conductor layer within a PCB may be determined from a microsectioned sample of the same. A small,non-functional area,e.g. a corner of the PCB,can be removed,and the surface roughness of the circuit layers can be assessed without impairing the function of the PCB.
In the proposed method,a conductor (a trace or a plane) in the microsectioned sample is first digitally photographed at high magnification. The digital photo obtained is then used as an input to a signal- and image-processing algorithm within a graphical user interface (GUI). The latter automatically computes and returns the surface roughness values of the layer photographed. The tool enables the user to examine the surface textures of the two sides of the conductor independently. In the case of a trace,the composite value of roughness,based on the entire perimeter of the trace cross-section can be calculated.

The latest status of new ED copper foil developments is presented: ultra-flat profile for high speed digital boards and ultra-thin foil for finest pitch applications.
Copper surface roughness has become a significant factor influencing the losses in high speed PCBs,particularly as they move into the 10 GHz range and above. A new base foil has been developed which achieves very smooth surfaces.
The combination of the new base foil types and new fine pitch treatments increases the active surface between copper and resin,providing reliable bond strength to proprietary resin systems used for low loss applications.
Ultra-thin foils down to 2µ have been developed for modified semi-additive technology enabling the PCB producer to achieve finest pitch,down to L/S of 20µ/20µ as required in the latest IC-Packaging generation and for flexible printed circuits.
Combined with a proprietary primer resin coating,these new generations of ultra-low profile foils are designed for both,high speed applications and high density boards by increasing the bond strength on low loss and high TG resin systems.

The PCB industry has advanced significantly in the recent millennium. OEM specifications and requirements have also advanced due to the maturing technologies. With this the requirements of Electrical Test of these higher technology products has advanced as well. Long gone are the “Pin in Hole” technology PCBs now surpassed by the large multilayer,blind/buried and Rigid Flex technologies. For the suppliers of Electrical Test,be it “in-house” or sub-contracted the industry specifications can be confusing,and at times non-comprehensible. The OEMs direct the IPC specification (6012,9252A,AS9100,etc) for their fabrication to the manufacturer but do the OEMs/CMs really understand what they are asking? There are many variables associated with these specifications and requirements to their designated classes regarding Electrical Test. OEMs decide what IPC class they wish their product manufactured due to performance requirements but overlook the electrical requirements associated with those requirements. Manufacturing,plating,etching and all those processes may be within the class requirements they require but they overlook the Electrical Requirements associated with their required IPC class. This paper will outline and define what requirements must be adhered to for the OEM community to truly achieve the IPC class product from the Electrical Test standpoint. This will include the test point optimization matrix,Isolation (shorts) parameters and Continuity (opens) parameters. This paper will also address the IPC Class III/A additional requirements for Aerospace and Military Avionics. The disconnect exists between OEMs understanding the requirements of their specific IPC class design versus the signature that will be presented from their design. This results in many Class III builds failing at Electrical Test.

Functional circuit test (FCT) of circuit boards and end products in a high volume (>1000 units per day) production environment presents challenging technical,logistic and cost obstacles that are usually more complex than those encountered at the inspection (automated optical inspection) and the manufacturing process test step (in-circuit test).
FCT “logistic challenges” are even more significant when there is a variety (high mix) of different circuit types to be tested. It is not uncommon for production lines to routinely have fifty or more active board types,each with a difficult-to-forecast production schedule that must respond to varying customer demand.
The exigencies of high volume production—not to mention the economics—preclude the typical “one-off” functional testers or “product-minus-one” found in many production environments. A “universal test system” is required. However,most “universal testers” are typically large and expensive,where (1) cycle times may be several times longer than the line takt rate,and (2) complex fixturing and UUT connection requirements that are difficult to modify in line further impede throughput.
Developing and maintaining revision control of application test programs for FCT is a further complicating factor in a high product mix environment. The difficulty of developing a practical FCT system to be used in the production line is exacerbated when the tests must include accurate and repeatable measurement of “outlier” electrical parameters such as very low or very high voltages and currents,and/or low level and/or very high frequency RF signals.
We have developed a standardized FCT system architecture,combined with fixturing/UUT interconnection solutions designed for the rigors of a high-mix,high volume production environment,significantly reducing total cost compared to typical custom-designed FCT systems. We have also developed algorithmic programming techniques that have proven useful to minimize overall UUT test time.
We will describe how this architectural and procedural approach meets FCT technical,logistic and economic goals by studying the actual functional test of a high-mix,high volume AC driver product,which has more than 50 distinct variations,built in a volume exceeding one million units per year.
The robustness of our technical test solution will be further illustrated by describing test requirements that included voltage measurements of up to 1200V and current measurements up to 40A.

As the need for electronics,electronic components and printed circuit boards becomes more important; the testing of products for these industries becomes a critical component. New materials,new components and new processes all play a vital role in the growth of the electronic and printed circuit board markets. Understanding the industry test guidelines and requirements are essential to product safety and product development. This presentation will give relevant information and guidance to the interconnection industry on what to look for in product testing. We will review industry test requirements and standards along with typical electronic company test standards for their products. Additionally the presentation will cover proper chamber selection,correct testing set up,air flow design and best test practices for the industry. With new markets and products being developed at a rapid pace; industry and company test standards will become part of what each manufacturer must understand. New test standards will be developed to secure both safety and industry guidelines that manufacturers must follow. As manufacturers develop new products for their markets; engineers,R&D managers,quality managers,product managers and product testing personal will need to be educated and knowledgeable of the testing guidelines so they can engineer,specify and build their products around these test standards. This presentation will give them a solid background in awareness of testing,testing requirements and testing standards.

Conformal coatings are considered a method of providing corrosion protection to electrical assemblies used in high-humidity or harsh environments. They are applied to PCBs for various reasons: to protect from moisture and contamination,to minimize dendritic growth,to provide stress relief,and for insulation resistance. These contribute to more durable handling,enhanced device reliability,and reduced warranty costs. Increased miniaturization of new circuit board designs requires flexible,low stress coating material to protect delicate components and fine-pitch leads. Silicone conformal coatings offer many advantages that address the general trend of ongoing PCBs designs,such as: high flexibility and low modulus to reduce stress on delicate or small components; high humidity resistance; wide operating temperature range that makes them suitable for extreme temperature cycling applications; excellent electrical properties; UV resistance; good chemical resistance,and adhesion to many common substrates used in electronics. Printed circuit board (PCB) coupons coated with three different silicone conformal coating formulations were exposed to temperature/humidity/bias conditions (85 °C / 85% RH/ 50 v) for 500 hours in order to evaluate the effects of conformal coating on surface insulation resistance (SIR). The goal of SIR testing is to identify possible failures in the functioning of printed circuit boards due to electro-chemical failure mechanisms,such as unacceptable electrical leakage under high humidity conditions,corrosion and metal migration,before they can occur on actual parts in the field. Results from this SIR testing are reviewed and discussed through this paper.

With the advent of RoHS and WEEE and the concern of some companies to eliminate halogen-containing compounds from their products,it is vital to have an understanding of halogen compounds and how to detect them. Halogens are a series of nonmetal elements from Group 17 in the periodic table. These elements are fluorine,chlorine,bromine,iodine,and astatine. A halide ion is a halogen atom bearing a negative charge. Halides can be part of the flux activator system that aid in oxide removal in either a solder paste or flux for wave soldering.
Halide content can be determined by qualitative or quantitative tests. The silver chromate method is a quick and inexpensive qualitative test method used to determine halides in a flux. This test is performed by placing the flux on silver chromate test paper. The halides in the flux react with the silver chromate and produce a characteristic color change on the test paper. A quantitative measure of halides is done by ion chromatography. This quantitative test is quite expensive and time consuming.
Test methods have also been developed to determine the activity of the fluxes in solder paste and wave solder. Most commonly used are the copper mirror and SIR (surface insulation resistance) tests. Copper mirror testing determines the activity of the flux by the effect the flux has on bright copper mirror films which have been vacuum deposited on clear glass. Based on J-STD 004B,the flux can be classified based on its activity levels as determined by this test.
SIR is an electrical test that measures a change over time in the electrical current between electrodes on the surface of a PCB. It is performed at high temperature and humidity levels,typically 85°C and 85% RH. Ionic residue,left on the PCB after reflow,from flux activators may cause low (i.e. poor) SIR readings.
This paper will discuss the theories behind these test techniques,their differences,and how the presence of halides in the flux activators will affect the SIR and copper mirror results

The overall effectiveness of 20 circuit board assembly processes,made up of 4 solder/flux combinations and 6 cleaning processes was investigated by using in-situ surface insulation resistance measurement,resistivity of solvent extract test,ion chromatography test,and optical inspection. The cleanliness of each process was represented by one board produced according to the IPC B-52 layout and design. Together with 4 unpopulated control boards,24 boards in total were investigated. Surface insulation resistance test evaluated the propensity of a printed circuit board to develop leakage currents and undergo metal migration when subjected to temperature-humidity-bias conditions of 40°C and 90 ± 3% relative humidity (consistent with IPC TM 650-2.6.3.7) and 5 V. The resistivity of solvent extract test inspected the cleanliness of a printed circuit board by extracting the ionizable surface contaminants and quantifying them in terms of an equivalent amount of sodium chloride. The ion chromatography test identified the specific types and amounts of ions present on the surface of a printed circuit board. Optical inspection was a visual check of the cleanliness and possible defects associated with manufacturing processes. By taking into account all the results of the 4 methods,this study clearly shows a relative ranking of the 20 samples provided,and a pass-fail assessment of the 20 processes. A good correspondence between surface insulation resistance and surface contamination levels was observed. The conductivity of the extract was consistent with the presence of ion types and concentrations,especially inorganic anions. This study also indicates that a good solder/flux combination must be paired with an appropriate cleaning process in order to be successful.

This paper explores the behaviour of a copper test vehicle with multiple reflowed solder joints,which has direct relevance to ball grid arrays (BGA) and high density interconnect structures. The paper explores the relative stress conditions on the distributed joints and the sensitivity to ball joint shape. The joints were exposed to isothermal fatigue,which was produced by a mechanical load that induced a cyclic shear stress across all the joints. The same structures were modelled using finite element analysis. The loading response distribution profile through the joints was analysed. The regions of likely failure were identified to be along the shear band and at the stress concentration areas in the corners of the joints. Failure of the individual joints was analysed by quantifying the accumulated creep strain per cycle. Solder joint models of three different shapes were investigated: rectangular,convex and concave shapes. This analysis has shown that less damage is found in concave shaped joints,indicating that BGAs would have more damage than the rectangular joints tested here. Results have also shown that more damage occurs in the outer joints as a vertical component appears due to a turning moment on the copper test vehicle. This behaviour could affect the external joints of large components,where the same vertical stress component may arise due to the differential CTE of the PCB and BGA component.