Over the years,the EU RoHS restriction and lead-free capability is the hottest environmental protection subject. In technology trends,signal integrity performance gets more critical based upon today’s higher signal transmission speed demand in every field of applications such as computer CPU and GPU chipset levels,system operation frequency and a variety of communication bus and cables like PCI express,SATA II and AGP bus for computer systems. Signal communication speed will shift from 1-5 Gbps range up to 5-10Gbps depending on applications. In order to meet lead-free
requirements and severe processes conditions with good signal integrity performance,the laminate material will play a more and more critical and sensitive role in the system.
From consumer products to high-end applications,there is a need for certain electrical and thermal performance; it is essential to meet those requirements with cost effectiveness. As a base material supplier,we will hereby discuss material design and factors that influence signal integrity,including epoxy and hardener,resin chemical construction,laminate ply-up construction,amount of resin content,fabric weaving density,moisture pick-up and environment factors etc. for a massive mainstream application and low loss application under the hypothesis of lead-free capability.

For companies that choose to take the Pb-free exemption under the European Union’s RoHS Directive and continue to manufacture tin-lead (Sn-Pb) electronic products,there is a growing concern about the lack of Sn-Pb ball grid array (BGA) components. Many companies are compelled to use the Pb-free Sn-Ag-Cu (SAC) BGA components in a Sn-Pb process,for which the assembly process and solder joint reliability have not yet been fully characterized.
A careful experimental investigation was undertaken to evaluate the reliability of solder joints of SAC BGA components formed using Sn-Pb solder paste. This evaluation specifically looked at the impact of package size,solder ball volume,printed circuit board (PCB) surface finish,time above liquidus and peak temperature on reliability. Four different BGA package sizes (ranging from 8 to 45 mm2) were selected with ball-to-ball pitch size ranging from 0.5mm to 1.27mm. Two different PCB finishes were used: electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) on copper. Four different profiles were developed with the maximum peak temperatures of 210oC and 215oC and time above liquidus ranging from 60 to 120 seconds using Sn-Pb paste. One profile was generated for a lead-free control. A total of 60 boards were assembled. Some of the boards were subjected to an as-assembled analysis while others were subjected to an accelerated thermal cycling (ATC) test in the temperature range of -40oC to 125oC for a maximum of 3500 cycles in accordance with IPC 9701A standard. Weibull plots were created and failure analysis performed.
Analysis of as-assembled solder joints revealed that for a time above liquidus of 120 seconds and below,the degree of mixing between the BGA SAC ball alloy and the Sn-Pb solder paste was less than 100 percent for packages with a ball pitch of 0.8mm or greater. Depending on package size,the peak reflow temperature was observed to have a significant impact on the solder joint microstructural homogeneity. The influence of reflow process parameters on solder joint reliability was clearly manifested in the Weibull plots. This paper provides a discussion of the impact of various profiles’ characteristics on the extent of mixing between SAC and Sn-Pb solder alloys and the associated thermal cyclic fatigue performance.

Since the European 2002/95/EC RoHS directive enforcement on 1st July 2006,a dominating part of the electronic industry suppressed the use of Pb in electronic equipment. As one of the consequences,exempted industries like avionics,military and telecom servers are facing increasing SnPb component obsolescence issues. Before transitioning to the qualification and deployment of full lead-free for AHP electronic products,reliable backward solutions are urgently needed to overcome SnPb package procurement difficulties. The main concerns lie in Pb-free BGAs and SnBi leaded packages assembled with a conventional SnPb reflow soldering process which affects the solder joint microstructure and can compromise the 2nd-level reliability.
This paper deals with an extensive cooperation program between an EMS and an equipment maker engaged to evaluate the use of a specific “SnPb+” assembly process as an option to solve the backward compatibility issues inherent to these kinds of components. The SnPb+ process window as well as the incidence of reflow conditions on BGA mixed interconnects have been studied for a variety of generic components ranging from large plastic- and ceramic-BGAs down to 0.5mm pitch CSPs. The reliability has been assessed with statistics in comparison to full SnPb both under thermo-mechanical and mechanical stresses (vibrations,shocks) focusing on mission critical high-end applications in harsh environments. Numerous failure analyses have been conducted to evidence the failure modes and support the obtained reliability data.
This paper presents the –55°C/+125°C ATC reliability results of mixed BGAs assembled under various reflow conditions on dedicated test vehicles reflecting typical functional boards with the PCB finish as a variable (ENIG and Immersion Sn).
As a conclusion,results indicate that SnPb+ is a very promising industrial solution for complex assemblies with long term mission in severe environments. Completion of the overall program including mechanical testing will permit to fully validate the use of the SnPb+ process to secure the backward transition phase.

Immersion silver chemistry has been promoted as a final finish for solderability for several years now. There are different commercially available products that will deposit silver in a wide range of thicknesses. Some chemistries,because of their very aggressive nature can produce a thickness distribution within a circuit board of 20-30 millionths and higher on small pads versus large ground planes. A large difference in silver thickness will affect solder wetting times within the same board especially with SAC alloys. A large variation in silver thickness can be overcome in assembly. But it typically requires a more precise assembly process with a longer and or hotter soldering profile.
A study has been underway evaluating nitrate based immersion silver chemistry against other potential silver sources. The study evaluated several types of additives against PCB design. Data on thickness distribution,copper attack rate,and deposit porosity has resulted in new theories on how to control immersion silver deposits. Specific formulas have been found that provide a pore free deposit with minimal attack on electroless copper. A specific test vehicle was chosen that takes into account ground planes,isolated traces,interconnected pads and different metallization processes. Data on thickness distribution,copper attack rate,and deposit porosity has resulted in new theories on how to control immersion silver deposits. Specific formulas have been found that provide a pore free deposit with minimal attack on electroless copper.

Concerns
There are some areas that must be accepted if planning to run the newest SENIG process:
- Slower plating rate in nickel (to get 150µ“ it will take 20 minutes)
- It works better at higher temperatures (190°F is best operating temp)
- It has higher phosphorus in the deposit (as high as 11.7%) and some evidence suggests solderability may be reduced at such levels; we have an extensive solderability study on-going.
Advantages
It is possible to have a high phosphorus nickel bath last to 5 MTO’s while running SENIG. The obvious advantage of longer bath life is also bolstered by other benefits:
- No dummy panels
- No minimum loading
- No corrosion from stripper or OSP cycles
- Pass SO2 testing

It is known that pure tin will undergo an allotropic transformation below 13°C where it becomes a semiconductor with a 26% [1,2] volume increase,and in appearance turns from a bright shiny metallic material,white ß tin,to a dark blue/grey dust,a tin. Such a transformation for an electrical interconnect is disastrous,if it were to occur in any of the high tin lead-free alloys it would be a catastrophe. The elimination of lead,one of the best elements to arrest the transformation process,has resulted in a number of high tin content alloys about which the potential to transform is unknown. Environmental factors that may enhance or arrest the rate and the incubation period of the transformation processes are also unknown. Due to the optimal transformation temperature of approximately –35°C and the long time required for the transformation,a direct observation of the phenomenon has not been possible. This study proposes a new method for observing the ß/a transformation in situ using a time-lapse photographic technique. This study concentrates on pure tin,but the applicability of the method opens new possibilities for studying the phenomenon for other tin alloys,such as the two commonly encountered eutectics of SnCu and SnAgCu. The transformation progressed radially from the inoculation point,starting at the surface. Propagation into the bulk occurred by peeling; with the external layers tending to “roll out” due to the volume expansion of the internal layers. In the meantime,cracks parallel to the propagation direction formed. Typically a pure tin sample would completely transform in just over 24 hours.

This paper reports the results of an evaluation of tin mitigation processes for components,i.e. converting parts with pure tin (Sn) and other lead-free (Pb-free) finishes to tin-lead (SnPb) finishes.

As early as 2001,leading cellular phone manufacturers had established stable assembly processes that were RoHS compliant for their cellular phone products. Since this time,the products manufactured on these lines have demonstrated equal or better
quality and reliability as compared to cellular phones assembled with tin-lead solder and non-RoHS compliant components. This success may have created the belief that there are few issues remaining in RoHS compliant assembly. This belief is far from the truth. Organizations that need to assemble a wide range of large,thick printed wiring boards (PWBs) continue to have considerable process challenges. These difficulties – combined with the need to assemble RoHS 5 (tin-lead solder paste and components with tin-lead finished leads,the remaining hardware being RoHS compliant),RoHS 5.5 (RoHS 5 with BGAs that have SAC or SACX solder balls) and RoHS 6 (fully compliant RoHS assembly) in one facility – create not only assembly technical challenges,but considerable material handling and logistics issues.
This paper is a review of the work done at Jabil in Billerica,Mass.,to address these challenges. An overview of the process development work in stencil printing,component placement and reflow soldering that was required to develop optimized assembly processes for PWBs with dimensions exceeding 56 cm and thicknesses approaching 0.3 cm will be discussed. The methods developed to handle the logistics issues of having RoHS 5,RoHS 5.5 and RoHS 6 assembly in one facility will also be presented.
The paper will conclude with a review of several of the products currently being assembled with these processes and logistics.

In this report,BGA packages with conventional and green material combination were selected as test vehicles for the investigation of MSL/temperature rating at the packaging level. The IC packaging was also tested at the package level and raw material level to show its RoHS6 compliance. Furthermore,chemical substances testing for halogen and Sb/Sb2O3 show a higher level of green compliance.

The proper grounding of all conductive items in the production workplace is an essential element of ESD (electrostatic discharge) management. ESD damage to components and assemblies in manufacturing is getting more and more attention. Smaller geometry and faster speeds of semiconductors have resulted in devices with increasingly higher ESD sensitivity. A typical sensitivity of integrated circuits and other devices is now in a 100V CDM range and many of the devices are already in 30 to 50V CDM sensitivity range. CDM stands for charged device model,and is defined as when a small device suspended by either pick-and-place vacuum picker or tweezers is charged and then is placed on a printed circuit board (PCB) making electrical contacts to the traces on the board and generating rapid discharge that can be quite harmful. Even if the device itself is not charged,a PCB or any other metal surface on which the device is placed,such as the shuttle in the IC handler,can be.