Many flat panel display technologies were developed and commercialized since 1980s. Today,liquid crystal display panels
(LCD) and plasma display panels (PDP) have the lion’s share of the large size flat panel displays,but there may be some new contenders waiting in the wings. There is a demand to produce even thinner large panel displays,or even make them flexible. The organic EL display (OLED) is one of the new display technologies engineers developed. OELD is successful in reducing the thickness of the flat panel TV; however,OELD’s manufacturing costs is much higher compared to LCDs or PDPs because of a long complicated photolithography process and expensive fluorescence materials required during production.
The solution is to use a screen-printing process that is capable to generate patterns with fewer steps compared photolithography and etching process. A series of advanced screen-printing process were developed to build functional circuit constructions for both active and passive components. In this study,the advanced screen-printing technology was applied to generate low electronic fluorescence patterns on flexible substrates to show the possibilities of low cost flexible displays.

In today’s manufacturing world,higher equipment utilization and lower operating cost is the way forward. Newer machineries are usually well equipped to get the job done as they are manufactured with the latest available technology whereas the earlier generation equipments are usually phased off or go through a series of improvements to meet the goals but at the expense of higher cost. The RFS handler is a good example of older generation equipment,making an impact with the help of TRIZ or Theory of Inventive Problem Solving in this ever demanding manufacturing world.
The Cone area of the RFS handler is made up of 2 perpendicular chuck heads that is used to pick up units (vacuum strength) from a horizontal position,rotates 90° and sockets the unit vertically at the TIU (Tester Interface Unit) for electrical testing. However,the many connections present from the vacuum generator right up to the suction cup of the cone chuck,cause the suction strength to be low. This,coupled with the centrifugal force of the rotating chuck,causes the unit to potentially drop,leading to high assist and downtime. In addition,we see that the high maintenance cost of the RFS handler is specifically coming from the Nest.
By adopting TRIZ,we used 2 concepts to solve the issues faced. Merging was used to solve the many connection problems present by removing the excessive components through the trimming process. There was also a change in suction cups. By doing so the suction strength has doubled without even changing the vacuum generator and the number of missing unit cases has reduced significantly by 82 %. The Cone related jams has reduced by another 78 % which in other words increases the Mean Time Between Assist by 120 %. Next,we used Segmentation for the Nest. The Nest being an ESD sensitive material is one of the most expensive consumable parts in the handler. By breaking the Nest up into 3-pieces,we now only change the affected part that is worn off and not the whole piece. This simple modification together with the change in suction cup helps us save 35 % on our monthly Preventive Maintenance cost. In the larger picture,we are looking at a projected savings of >US$800K throughout other Intel sites.

With greater time to market and time to volume pressures,manufacturers of populated printed circuit boards have traditionally relied upon un-powered vectorless testing to quickly and reliably identify open pins on integrated circuit devices and connectors that reside on populated PCB assemblies. Unfortunately with the advent of higher speed signals,PCB designers can no longer tolerate the negative transmission line effects of test pads that are used to gain electrical access during in-circuit testing. An improved vectorless test method has been developed to address the loss of test coverage on high speed signals that reside on contemporary printed circuit board assemblies. This technology can quickly and effectively identify open connections between a boundary scan based device and other connected devices including a non-boundary scan device,a connector,or a socket. A discussion of this new vectorless test method,employing virtual access,is the focus of this paper.

The areas of entrapment on cleaned and no-clean assemblies are showing higher levels of contamination around BGA’s,in microvias and particularly under components like the QFN. Flux residues trapped under and around low standoff components that are causing leakage paths are negatively impacting field performance,and are showing up as no trouble found return more often than ever. Microvias are corroding open during soldering due to the contamination from fabrication found in vias from the etch steps and poor cup rinsing of the plugged vias. This paper will cover techniques for investigating pockets of contamination using a localized extraction method and ion chromatography analysis to establish root cause,and the development of corrective action plans for field failure projects. Defining,implementing and monitoring corrective action plans for the failed assemblies has allowed us to understand the processing variables,and optimize the critical parameters that meet the performance needs of today’s technology.

Moore’s Law infers that the number of transistors on a chip doubles approximately every two years. Consistent with Moore’s Law,high reliability electronic devices build faster processing speed and memory capacity using increasing smaller platforms. The trend toward highly dense assemblies reduces the spacing between conductors while yielding a larger electronic field. As the industry moves to higher functionality,miniaturization,and lead-free soldering,studies show that cleanliness of the assembly becomes more important. Residues under low standoff components,with gaps less than 2 mils,represent an increasingly difficult cleaning challenge. Collaboration from cleaning equipment and cleaning material companies has led to innovations for improving throughput and complete residue removal under low standoff components. The purpose of this paper is to report both mechanical and chemical innovations that open the process window.

As the electronic industry moves to lead-free assembly and finer-pitch circuits,widely used printed wiring board (PWB) finish,SnPb HASL,has been replaced with lead-free and coplanar PWB finishes such as OSP,ImAg,ENIG,and ImSn. While SnPb HASL offers excellent corrosion protection of the underlying copper due to its thick coating and inherent corrosion resistance,the lead-free board finishes provide reduced corrosion protection to the underlying copper due to their very thin coating. For ImAg,the coating material itself can also corrode in more aggressive environments. This is an issue for products deployed in environments with high levels of sulfur containing pollutants encountered in the current global market. In those corrosive environments,creep corrosion has been observed and led to product failures in very short service life (1-5 years). Creep corrosion failures within one year of product deployment have also been reported. This has prompted an industry-wide effort to understand creep corrosion although minimal progress has been made in this effort. This lack of progress has been primarily due to the inability of reproducing creep corrosion in the lab using realistic accelerated aging tests. In this paper,we will demonstrate that creep corrosion on a PWB is highly surface sensitive. Neither clean FR4 nor clean solder mask surfaces support the creep corrosion. In general,the board assembled with rosin wave soldering fluxes and solder paste containing rosin flux is also resistant to the creep corrosion. However,residue left on the solder mask surface by organic acid flux is highly active and supports the creep corrosion of copper sulfides. The proper choice of the assembly flux can eliminate product failure due to creep corrosion associated with the ImAg plated circuit boards deployed in highly corrosive global environments. Furthermore,mixed flowing gas testing (MFG) provides a realistic accelerated test for simulating the creep corrosion in the laboratory without requiring condensing conditions.

Although the advantages of Hot Air Solder Leveling (HASL) in providing the most robust solderable finish for printed circuit boards are well recognized,in the years leading up to the implementation of the EU RoHS Directive in July 2006 the conventional wisdom was that it would have no place in the new lead-free electronics manufacturing technology. The widely promoted view was that HASL,which had been the most popular printed circuit board finish in North America,Europe and most of Asia outside Japan during the tin-lead era,would be largely replaced in the lead-free era by Organic Solderability Protectants (OSP) and immersion silver with perhaps a minor role for immersion tin. This view was reinforced by some early trials of lead-free HASL in which the tin-silver-copper alloy,then promoted as the universal lead-free replacement for tin-lead,was used as the coating alloy. The aggressive dissolution of copper by that alloy and its non-eutectic behavior made it difficult to use and to get satisfactory results. In the meantime,however,in Europe a microalloyed tin-copper alloy with low copper dissolution and eutectic behavior was evaluated and found to yield promising results. A smooth mirror-bright finish could be achieved on existing equipment with process temperatures that existing laminate materials could accommodate. An unexpected advantage was that the thickness of the lead-free HASL finish was more uniform than typically obtained with tin-lead so that it could be used in applications previously excluded to tin-lead HASL because of concerns about coplanarity,e.g. pads for BGA,CSP and fine pitch QFP. By July 2006 there were nearly 200 lead-free HASL lines running in Europe and that number has continued to increase since then. In response to demand by European customers many Chinese printed circuit board shops have installed lead-free HASL and there are now lines operating in South East Asia,India and North America. As problems have been encountered with OSP and immersion silver finishes electronics manufacturers have looked to lead-free HASL as a solution. In the more than 5 years in which the lead-free HASL process has been used in commercial mass product much has been learned about the operation of the process on the optimization of results. In this paper the author will report on current best practice on the operation of lead-free HASL lines and the properties that can be expected of a properly applied lead-free HASL finish.

Within today’s Consumer Electronics Industry,a laboratory report listing elemental content is standard protocol. Understanding the information listed within a lab report can be difficult and understanding how that information was obtained is not common knowledge.
- Do you know what the Laboratory sample preparation techniques are?
- Is the Laboratory using the correct test methods?
- Does the Laboratory have the proper certifications?
- How interactive are you with the Laboratory?
Understanding the answers to these questions is imperative to showing compliance to the various global eco-compliance
directives and OEM “Green Programs” such as EU RoHS,China RoHS,REACH,Halogen Free,etc.
This paper will provide insight into laboratory protocols and practices. It will provide information on the appropriate
certifications a testing laboratory should have. It will also try to make clear how to interpret the information on a “lab report”
and explain terminology such as:
- MDLs
- PQLs
- Units of measure (mg/kg,ppm,etc…)
- LCS and LCS recoveries
- QC protocols
- Flags
- N.D. vs <
The paper will also discuss test methods specific to the various global eco-compliance directives as well as the different
instrumentation used for these types of analyses.
Lastly,this paper will discuss the importance of building a “partnership” between the laboratory and the Client. Due to the
diverse array of sample matrices as well as the various manufacturing procedures within the consumer electronics industry,
the need of a synergy between the Laboratory and the Client is a very important component of a company’s compliance strategy. It will also explain why sample preparation is more important than the actual testing of a sample and provide some examples of “issues” that are inherent to material testing.
The premise of this paper is to give a brief overview of laboratory protocols and practices,provide some answers to questions that you have and that we have been hearing,provide terminology/acronyms and their definitions,try to explain how to
interpret the information on a “lab report”,and try to increase your knowledge of what a Laboratory can provide. The topics we will cover are Accreditations,Acronyms/Terminology/Definitions,Lab Reports,Methods/Instrumentation,Sample Preparation,and criteria to consider when choosing a lab.

The following article is a series of “from the trenches” stories,taken both from the perspective of an electronics manufacturer and an environmental compliance consultancy. The accounts below provide a library of RoHS compliance scenarios that illustrate the extremes of building an RoHS compliant product and the pitfalls of assuming that a declaration of compliance is iron-clad.
Unlike most papers,portions of this one are written in first person. In order to preserve both the confidentiality of our sources and the integrity of this paper,all external stories provided to us have been copied into the paper and kept anonymous. This allows for a non-biased and often humorous accounting of RoHS.

Embedded passives,especially embedded resistors and capacitors have been a hot topic since the mid-to-late 1990s. It is easy to understand why they have generated so much interest. Technology continues to be driven by performance,space and cost. Embedded passives offer potential significant advantages in each of these areas.
Embedded passives have far less parasitic inductance than discrete components,which enables electrical performance advantages (noise and EMI reduction),especially in high speed digital applications. Embedding passives saves surface real estate,which allows for board size reductions which is critical in space constrained designs such as military/aerospace and portable products. The incremental cost of embedding additional passive components is typically negligible; this offers the potential for system cost reduction in designs with high passive component counts. Embedded passives also offer additional advantages such as improved reliability and weight reduction due to the elimination of vias and solder joints.
However,even with all of their potential advantages,high performance embedded passive materials remained a niche market
until the last couple of years. There were a number of reasons for this,including the typical fear of new technology,limited technical resources and funding,lack of successful case studies,lack of an experienced supply chain,lack of long term reliability data,very limited physical layout and simulation/modeling software tools,improvements in existing discrete passive products,the telecom bust,cost concerns and an insufficient knowledge of intellectual property and prior art.
After more than 10 years of large scale interest,high performance embedded resistors and capacitors have finally become mainstream technologies in many market segments. There are multiple suppliers of commercial thin film metal resistor materials and ultra thin embedded capacitor materials. A large number of PCB fabs across the globe have very significant experience in processing these materials in moderate to high volumes.
This paper will look at the above barriers to the implementation of high performance embedded passives,focusing on embedded capacitor laminate materials,and show how these barriers were overcome so that embedded passives could finally become a mainstream technology.