Testing DDR memories on Printed Circuit Boards has steadily gotten more difficult. Most such memories do not have any on-chip Design-for-Test features. Adequate test access is a disappearing luxury. It is a challenge to present these memories with the critically timed protocols they require to work at all,and,to participate in their test. While Boundary Scan technology (in the memory controller devices) can assist with the access problem,it is increasingly difficult to achieve the required protocols in the serialized environment of Boundary Scan.
DDR memory vendors have been loath to provide on-chip test assistance (DFT),but one example of a graphical RAM with DFT does exist. There is also a newly published IEEE Standard 1581 that offers a way to add DFT to RAM devices,with or without adding new pins to the device. These capabilities dramatically reduce the difficulty in creating stable,reliable,repeatable tests for DDR memories at board test.
The presentation will include a discussion of the DDR memory challenges we see today,and how the adoption of DFT capabilities pays off in higher test coverage,better diagnostics and reduced programming/support time.

Increased pressures to reduce time to market and time to volume have forced many manufacturers of populated printed circuit boards to rely on capacitively coupled,un-powered,vectorless in-circuit test techniques to identify open pins on ICs and connectors. Unfortunately,faster signals and higher-density printed circuit boards (PCBs) have placed pressures on designers to reduce the number of test pads that provide electrical access for vectorless test techniques.
A powered-up test solution using boundary scan as the stimulus generator and a capacitive sensor plate for detection can address this loss of access. This virtual access method can quickly and effectively identify connectivity defects between boundary scan based ICs and other devices,including non-boundary scan devices,connectors,and sockets that lack physical test access.
This test approach employs a novel set of time domain auto-correlation and cross-correlation algorithms that eliminate many of the restrictions associated with existing frequency domain alternatives. More specifically,this test method does not restrict the operating frequency of the boundary scan’s clock signal (TCK) or the number of scan cells in the boundary scan chain. Analyzing the temporal response of a single event pulse in the time domain by use of matched filtering eliminates the need to generate the narrow range of stimulus frequencies that traditional capacitive sensor plate methods require.
This virtual test method works with any boundary scan device that complies with the IEEE 1149.1,1149.4 or 1149.6 standards. A discussion of this test method as well as recent field data,lessons learned and obstacles overcome while implementing this technique on a high-end computer server product at a high volume production facility are disclosed.

The stencil printing process is one of the most critical processes in the electronic production. Due to the requirement: “faster and smaller” it is necessary to place components with different paste volume close together without regard to solder paste printing. In our days it is no longer possible to control the solder paste volume only by adjustment of the aperture dimensions.
The requirements of solder paste volumes for specific components are realized by different thicknesses of metal sheets in one stencil with so called step stencils. The step-down stencil is required when it is desirable to print fine-pitch devices using a thinner stencil foil,but print other devices using a thicker stencil foil.
The paper presents the innovative technology of step-up and step-down stencils in a laser cutting and laser welding process. The step-up/step-down stencil is a special development for the adjustment of solder paste quantity,fulfilling the needs of placement and soldering. This includes the laser cutting and laser welding process as well as the resulting stencil characteristics and the potential of the printing process. Influencing factors on the printing process for step stencils like squeegee speed,squeegee angle,squeegee pressure,squeegee material,printing direction and distance from the step-edge to the nearest aperture are shown in this paper. A test layout was developed with different step heights and different distances from the nearest apertures to the step-edge to give proposals and guidelines for future designs. The transferred solder paste volume was measured with highly sophisticated systems and the results which are gained in this study allow new design guidelines.
The focus of this paper is on the printing performance of step-up/step-down stencils and the paper ends up with a short outlook on 3D cavity printing.

Considering technological advances in multi-depth cavities in the PCB manufacturing industry,various subtopics have materialized regarding the processing and application of such features in device manufacturing.
In a previous paper the topic of solder paste printing on PCBs on standard SMT equipment and with multiple cavity depths was investigated. The success of solder paste printing is a prerequisite for further assembly and reliability of the entire electronic construct. In this paper we intend to examine the overall manufacturability and subsequently analyze the reliability of multi-depth cavity PCBAs,presupposing the presence of solderable features within these cavities.
The intended methods of evaluation for manufacturability will be the evaluation of solder paste volume (PV) and warpage performance.
The intended methods of evaluation for reliability will be the evaluation of mechanical loading (drop test) and thermal loading (TCT,reflow) on PCBA test vehicles.
The aim of these investigations is to identify any possible criteria of a solderable multi-depth cavity PCB,which may affect manufacturability and/or reliability,and if so to which magnitude. Thus,we expect to locate general and possibly specific advantages and/or limitations of such a product under a standard manufacturing environment.
In an effort to achieve a broader understanding of the entire process and product scope,the participants in the trial are an HDI PCB manufacturer,stencil manufacturer and a global EMS manufacturer.

With the miniaturization of components in the semiconductor industry,the need for specialized solder pastes with finer
powder mesh sizes for package-on-package (PoP) assemblies has become imperative and increasingly more common. As the
powder mesh size decreases (smaller diameter powder),more surface area of powder within the paste is exposed and,
therefore,more susceptible to oxidation. The flux vehicle of the solder paste consequentially has more oxides to remove in
order to allow for proper coalescence to form a good solder joint. The intent of this paper is to evaluate whether the decreased
powder mesh size and increased oxide content of the powder in the PoP pastes affects the voiding performance of the
materials,and to what degree.

The Surface Mount Technology (SMT) industry has been faced with several challenges in the past decades. Two of the most recent ones are RoHS compliant lead-free assembly and the adoption of fine-pitch components assembly processes. Moreover,halogen-free is another new requirement for assembled PCB reliability,environmental and health concerns. All these requirements create fundamental challenges of developing a solder paste to satisfy everything. One of the resolutions for these challenges can be the development of the activator package with the advanced organic chemistry technology.
Serial innovative activator system was developed recently for solder paste flux,tacky flux and liquid flux formulation. This paper will discuss three Type 4 lead-free halogen-free no-clean solder pastes (ROL0) developed based on different innovative activators,which respond to the challenges described above. The printing performance,coalescence,wetting,BGA voiding and head-in-pillow characteristics,are compared and discussed in detail. The testing results show all three pastes with the new activators are fully capable of printing and reflowing 01005 components with different board/device finishes,even in air reflow. They can handle a wide variety of print variables,including print speed,long abandon time and a wide range of temperature and humidity. Post-soldering,the paste offers minimized defects,including head-in-pillow and BGA voiding.

•What is Digital Printing
•Ink Jet Technology
•Printing SM using Ink Jet
- Highlights
- Zero clearance technology
- Product improvements
- PCB shops,end users and designers Benefits

- DD Detector is State of the Art
- Software: Addressing all measurement challenges; Measurement Results for Au,Pd and Ni(P),independent of substrate material
- Traceability and Reproducibility through Reference Standards
- XRF-Instrument considerations
- Comparison of Spectra

Atmospheric dust consists of solids suspended in air. Dust is well known for its complex nature. It normally includes inorganic mineral materials,water soluble salts,organic materials,and a small amount of water. The impact of dust on the reliability of printed circuit board assemblies (PCBAs) is ever-growing,driven by the miniaturization of technology and the increasing un-controlled operating conditions with more dust exposure in telecom and information industries.
A fundamental and systematic study on the impact of dust is needed,since not much research has been done in this area. We started by asking some basic questions on dust. Since dust is always present in the atmosphere,under what conditions is dust a reliability concern for electronics? What are the key characteristics of dust? Are some dust types worse than others: e.g.,dust that is more hydrophilic? Should there be classifications of dust? How will different combinations of dust,voltage,relative humidity (RH),temperature,and other factors affect electronic materials and circuits? This paper presents some results towards answering these questions. We designed a group of experiments using real life dust collected from both indoor and outdoor areas. AC impedance spectroscopy (IS) was employed as the measurement technique for this research. We designed test coupons with adjustable spacing between electrodes and measured their electric properties under different relative humidities. We analyzed aqueous solutions produced from dust samples were using their pH and conductivity. And we further analyzed the compositions of the dust samples. We found that dust had a significant impact on the reliability of PCBA. Relating the test results to the analysis results,indoor dust is more sensitive to the change of relative humidity compared to outdoor dust due to the water soluble salts and particle size. At the same dust deposition density,indoor dust is more susceptible to induce moisture related failure,such as loss of surface insulation resistance,electrochemical migration,and corrosion.

Silicone contamination is known to have a negative impact on assembly processes such as soldering,adhesive bonding,coating,and wire bonding. In particular,silicone is known to cause de-wetting of materials from surfaces and can result in adhesive failures. There are many sources for silicone contamination with common sources being mold releases or lubricants on manufacturing tools,offgassing during cure of silicone paste adhesives,and residue from pressure sensitive tape. This effort addresses silicone contamination by quantifying adhesive effects under known silicone contaminations. The first step in this effort identified an FT-IR spectroscopic detection limit for surface silicone utilizing the area under the 1263 cm-1 (Si-CH3) absorbance peak as a function of concentration (ug/cm2). The next step was to pre-contaminate surfaces with known concentrations of silicone oil and assess the effects on surface wetting and adhesion. This information will be used to establish guidelines for silicone contamination in different manufacturing areas within Harris Corporation.