During the design phase of a project,distribution of metal on the external layers of printed circuit boards is not a
consideration. System designers concentrate on implementing the required logic. PCB designers have to satisfy many
electrical and mechanical constraints and they do not lay out boards to provide an even distribution of metal on external
layers. This creates a difficult problem for the fabricator,who tries to evenly plate a board with uneven metal distribution. In
high-speed boards,uneven plating creates uneven impedance and circuit timing margins are decreased,negatively affecting a
circuit board’s performance.
In a plating tank,plating current is essentially constant across an entire panel being plated and all of the plating current must
be absorbed. Pads and tracks in an area of a board with low metal density will be plated more than the same pads and tracks
in an area of high metal density.
If a track originates in an area of high metal density and traverses an area of low metal density,its cross-section area will
change due to uneven plating. A change in cross-section area will produce a change in impedance and part of a signal
traveling along the track will be reflected. Reflections will cause a reduction in pulse amplitude,plus an increase in rise- and
fall-times. This will reduce circuit timing margins and may be the difference between a high-speed board working or not
working.
The best method of avoiding tracks with varying impedance is to equalize the metal distribution on external layers. Using
statistical analysis,the mean metal distribution is computed and thieving only added to areas below the mean to bring them
up to the mean. This provides a more even distribution of metal across a board,which will lead to better performance of highspeed
boards. Equalized plating will also make a board flatter,improving assembly yields.

Layout designers play a critical role in the design of high-speed circuits. In an optimized process,they take constraints
defined by engineering and create a layout that adheres to those design rules. Typically,however,the process is more ad hoc
with constraints being transferred via paper or voice,putting more responsibility on the layout designer to translate the
requirements and implement a functional design. In some organizations,engineering has taken over layout of high-speed
signals to ensure accurate implementation of constraints. Unfortunately,this often results in designs that are impossible to
complete or are un-manufacturable.
Today's complex designs can have advanced constraints on 80-90% of the board's signals,significantly increasing the layout
difficulty and design cycle time. To appropriately manage and implement these constraints,layout designers must
understand concepts such as differential impedance/signaling,star net topologies,interconnect delay and crosstalk coupling.
This paper will address:
• High-speed constraint categories in “electrical” and “physical” incarnations
• An optimized design process focusing on collaboration between engineering and layout departments
• Routing best practices to adhere to advanced high-speed constraints
• The impact/benefit of advanced fabrication technologies like HDI and embedded passives on high-speed design.

Whether based on good science or not,the elimination of lead from electronic equipment as a result of the European RoHS
legislation is a reality. Even those market segments with exemptions meant to last several years are being pushed towards
Lead Free assembly sooner than expected due to component availability concerns and constraints within the electronics
manufacturing services industry. The most common question asked of base material suppliers is ‘what laminate can I use?’
From the standpoint of ‘compliance,’ most laminate materials are acceptable. Most materials do not contain lead or the other
restricted metals. The brominated flame retardant used in most laminates is NOT restricted either. However,in terms of
‘compatibility,’ the answer is very complex. This is the result of several factors. First,PWB design and construction will
have a significant impact on the base material properties required. Thin,low layer count PWBs may have different
requirements than very thick,high layer count PWBs. Copper weights,aspect ratios and other design features will also have
an impact. End use application and the associated requirement for long-term reliability will also impact the decision-making
process. The requirements for a cell phone,video game or even a computer motherboard will be very different than those for
high-end servers,telecommunications gear,avionics,and critical medical and automotive electronics. Last,not all Lead Free
assembly processes are the same. Some designs will experience peak temperatures of 245oC while others will experience
peak temperatures of 260oC. Some PWBs may experience 2-3 thermal cycles,others up to 5-6,or even more depending on
how many reworks are allowed. All of this makes it impossible to recommend one base material for all applications without
either under specifying the laminate material and risking defects during assembly or later on in the field,or over specifying
the material and paying too much for the material or limiting availability. The purpose of this paper is to summarize the
critical laminate properties,present test data showing the impact of higher temperatures,and introduce a laminate material
selection approach designed to help answer the question regarding what laminate material should be considered for a given
application.

Supply chain readiness and compatibility are critical to a smooth transition to environmental compliance for the worldwide
electronics industry. This paper reviews the status of Lead Free soldering and RoHS compliance,supply chain readiness,key
compatibility issues and future challenges.

Meeting RoHS requirements is confusing at best. Currently,RoHS bans the presence of 6 substances,: Lead (Pb),Cadmium
(Cd),Mercury (Hg),Hexavalent Chromium (Cr6+),Polybrominated biphenyl (PBB) and Polybrominated diphenylether
(PBDE). As of 18 August 2005,the European Union (EU) amended the RoHS document with maximum concentration
values (MCVs) of 1000 ppm for 5 of the substances; Pb,Hg,Cr6+,PBB & PBDE and 100 ppm for the 6th substance; Cd at
the homogenous level. Other documents within the EU and member states have defined MCVs,but there is not total
agreement between EU Directives and the member states on the maximum threshold values. With the delay of defined RoHS
thresholds,other regions of the world are defining MCVs,but without universal agreement. Companies in the electrical and
electronics equipment (EEE) industry are subsequently incorporating their understanding of MCVs into company
specifications and requiring the suppliers to meet them.
What are the existing EU Directive requirements? How do they apply and what thresholds should be used for electrical and
electronic products? This paper will discuss the RoHS 6 substances,thresholds as stated in the EU,common company
defined threshold differences and the issues they cause. It is not all inclusive since laws and directives are constantly
changing,evolving or being released.

Portable electronic device circuit packs were ground up to more than meet EPA sieving criteria and were then subjected to
the well known EPA Method 1311 leaching protocol. Based on work from the previous study,mainly Fe,Ni,Cu,Zn,and Pb
were investigated. Leachate was also separately treated with egg whites and cardboard and the dissolved metal
concentrations were found to be significantly reduced. Individual spikes of 500mg Fe,Ni,Cu,Zn,and Pb (artificial leachate)
were run through columns of topsoil,sand,gravel,vermiculite and perlite to compare to the earlier work using topsoil,in a
continuing effort to show what might happen if leachate were to escape from a landfill.

The enactment of the Restriction of Hazardous Substances (RoHS) Directive is prompting significant changes in solder paste
formulations and their process conditions as manufacturers move to Lead Free electronics assemblies. The residues
remaining after reflow of these new Lead Free materials are proving much more difficult to remove. This study evaluates the
cleaning capability of aqueous,semi-aqueous,solvent,and vapor degreasing including co-solvent products and processes.
Lead Free eutectic solder pastes from three leading suppliers were selected and cleaning results were evaluated and results
are compared to leaded eutectic materials.

As the electronics industry moves toward the implementation of Pb-free soldering,the impact on the assembly process must
be considered. One process that is often over looked is the cleaning of assembled printed circuit boards. How will the
introduction of lead free material impact the cleaning process?
A number of studies have proven the poorer wetting of SAC 305 alloys and many of the other Pb-free alloys as contrasted to
Sn/Pb during the soldering process. To address this issue,solder paste manufacturers researched and advanced flux
technologies to improve soldering yields. Many of the advanced flux technologies employ modern “exotic” compounds,
which often increase the difficulty of removing post-soldering residues. It is evident that both cleaning equipment and
cleaning chemistry must be modified to enable effective and consistent cleaning of Pb-free flux residues. It is also evident
that the best overall cleaning solutions will be provided by cleaning equipment and cleaning material companies working
together to optimize their products.
This paper discusses extensive cleanliness testing of over 70 Pb-free soldering materials. The data suggests increased
difficulty when cleaning Pb-free post-soldering residues. Based on the data,this paper discusses advances in cleaning
material and cleaning equipment mechanical designs that will optimize the cleaning of Pb-free flux residues. This paper will
detail the changes made in the cleaning equipment for optimizing the cleaning material advancements in industry standard
cleaning equipment.

Cleaning prior to conformal coating ensures optimal adhesion. In fact,a number of contaminations that are created during the
soldering steps significantly impair the cross linkage and can be safely removed by an adequate cleaning process. Specific
analytical methods are therefore highly recommended in addition to standardized cleanliness test procedures. This article sets
out to reflect on the latest study conducted,highlighting for example the characterization of encountered contamination for
eutectic and lead-free materials as well as their respective impact on quality and reliability. It is noteworthy to already point
out that the use of lead-free products will make cleaning,prior to conformal coating,an even higher necessity.
There has been a clear and consistent increase in the demand for no-clean (eutectic as well as lead-free) products over the last
few years. This trend coincides – and is likely correlated – to the growth of observed in-field service failures,particularly
with coated assemblies.

A new organophosphorus curing agent,Fyrol PMP,specially designed for electronic thermoset resins was recently
introduced to the market. This paper describes the chemical structure and physical properties of this material. This curing
agent has a unique mechanism of cross-linking epoxy resins. Because of high functionality it allows achieving high Tg and
good thermal properties required for lead-free soldering. About 20 to 30 wt. % this material completely cures epoxy resin
and provides a V-0 UL-94 flammability rating in the copper clad laminates. The loading of the material can be decreased to
10 wt. % when it is used in the combination with alumina trihydrate (ATH). In typical FR-4 laminate formulations,a glass
transition temperature (Tg) of 150°C or higher can be achieved . Co-addition of benzoxazine resin raises the Tg to 190°C. The
laminates pass the Delamination Test at the temperature of lead-free soldering (288°C) and securely pass the Pressure Cooker
Test.