The constant drive by designers to create more functionally unique products has challenged the assembly community for
some time. As a result,many processes have been developed under the “Necessity is the Mother of Invention” rule. For EMS
providers to develop unique adaptations to their processes,they must work closely with their suppliers of equipment and
materials. Some requirements even push the scope of assembly outside typical boundaries demanding truly creative solutions.
Flip Chip applications are a good example of this technology. Instances whereby placement tolerances push the limits of
conventional SMT equipment,but volumes and specialization preclude the use of stand alone die bonding equipment are
becoming more common.
In order to match the true requirements of the process to the capability of the machine,a determination of factors affecting
the accuracy must be made. Specified placement tolerances are vague and may not apply in all instances as stated.
The process development does not end with getting the devices placed,but extends into determining an adequate metrology
for verification of the placement accuracy. Applications where the placement tolerance is less than 25 microns create new
challenges for measurement. Additionally,imaging of these devices may prove to be the most challenging piece of the
development.
The application covered in this paper involves the placement of 2 Flip Chip devices end to end with tolerances of ± 10
microns. The body of the discussion will cover the challenges of the application and how these were addressed through the
partnership of the EMS and equipment manufacturer. Details will be given on the technical solutions for imaging,
movement,tooling and measurement as well as final process data.

With the combination of increased product complexity,increased frequencies and ever decreasing component sizes and
pitches designers are faced with the dilemma on how design their products in the most cost effective manner possible. In
larger more complex products designers most often than not are creating “islands of densities” or daughter cards that join
onto larger and more complex boards. In order for designers to “link” the daughter cards to the motherboard designers are
using newly designed interconnect products. Interconnect suppliers have introduced products such as a BGA type board to
board connector. Advantages of this type of connector extend into the contract manufacturing realm as the connectors are
processed during the mass reflow of the assembly eliminating process steps such as wave solder or press fit operations. The
manufacturability of these connectors have been evaluated and documented in earlier reports but little data is available on the
second level testing and reliability of these connectors. This report focuses on the manufacturability and reliability of the
interconnects generated from accelerated thermal cycling of the “Metropolis” test vehicle (connector test vehicle). The tests
were performed using IPC-9701 as a guideline. The “Metropolis” test vehicle is populated with two styles of a BGA
mezzanine connector,a BGA mounted socket and two press fit connectors.

This paper addresses the effect of pulse plating of electronic interconnects for advanced electronic modules. This paper
builds on earlier work by correlating plating cell and tank design issues and tank characterization studies with standard
mechanical and reliability tests. The current work evaluates the resulting copper deposits in terms of throwing power,
mechanical and reliability tests and compares the results to a current state-of-the-art process. The present work relies on
electrical mediation for a highly controlled electrodeposition process that results in a very uniform and reproducible deposit;
selection of the electric mediation parameters is based on considerations of mass transfer as well as microprofiles and
macroprofiles related to current distribution. Data for plating industry test panels containing PTHs of approximately 5:1,
10:1,and 15:1 aspect ratios are presented. Using a pulse waveform sequence,throwing powers of approximately 90-100%
are observed at plating rates of approximately 20 ASF.

Nanocrystalline and ultra-fine grain copper can potentially offer increased reliability and functionality of printed wiring
boards due to expected enhancements in strength and achievable wiring density by grain size reduction. In this research inhouse
synthesized nanocrystalline and ultra-fine grain-size copper foils produced by pulsed electrodeposition were compared
with commercially available electronic grade polycrystalline electrodeposited (EG-ED) and cold rolled annealed (EG-CRA)
copper foil. The microstructures of all materials were characterized by transmission electron microscopy (TEM). Nanoindentation
and the four-point probe technique were used to evaluate their hardness and electrical resistivity,respectively. It
is shown that grain size reduction results in significant increases in hardness at a moderate loss in conductivity.

Continuous measling,or unidirectional crazing,was observed in a multi-layer polyimide printed wiring board following
assembly operations. Damage to the PWB preferentially followed the warp direction of the glass fiber reinforcement and
extended beyond the region of localized heating. Further investigation revealed that glass fiber pullout in cross-sectional
mounts is an indicator of laminate material that is prone to measling or crazing. Testing showed that boards with fiber pullout
were significantly more likely to show damage in base material in subsequent process,especially when a drying bake was not
recently performed. Damage to these PWBs consisted of cracks not between bundles of glass-fiber reinforcement,but within
individual bundles. These cracks may produce reliability risks in PWB.

Today both Interconnect Stress Test (IST) and Highly Accelerated Thermal Shock (HATS) test methods are used to measure
plated through hole via reliability. Both of these test methods have proved useful in their ability to quantify via reliability
and have gained a wide level of acceptance and credibility within the industry.
This paper covers the use of HATS testing to determine the long-term reliability impact of simulated higher temperature
assembly and rework thermal excursions. In particular,this paper will present data showing a complex relationship between
higher temperature assembly processing and rework cycles,and subsequent HATS and IST cycles to failure (CTF). The
Inverse Power Law (IPL) will be used to plot the via stress versus CTF relationship when cycling below the laminate material
glass transition temperature (Tg).

The surface finishes Ni-P/Pd/Au (hereafter referred to ENEPIG) and Ni-P/Au (hereafter referred to ENIG) were
prepared on ball grid array (BGA) circuit boards by electroless/immersion plating method. The IMCs (Inter metallic
compounds) of Sn37Pb and Sn3.0Ag0.5Cu solder with these finishes were compared using TEM (Transmission
Electron Microscope). It was found that the IMC crystal lattice is dependant on solder material and the solder joint
reliability is dependant on both the solder material as well as the surface finish. In using Sn3.0Ag0.5Cu solder,the Pd
in the ENEPIG finish limits the Ni diffusion and exhibits excellent solder joint reliability. In the combination of Sn/Pb
solder and ENEPIG,the Ni diffusion is accelerated and solder joint reliably is compromised.

Over the past ten years,two new test methods: Interconnect Stress Test [1] and Highly Accelerated Thermal Shock [2] have
been developed to perform thermal cycling testing and in particular,to measure plated through hole reliability. Both of these
test methods have proved useful in their ability to quantify plated through hole reliability and have gained a wide level of
acceptance and creditability within the industry. Along with more tradition air-to-air and liquid-to-liquid thermal cycle
methods,these two new test methods expand the test methods available to the interconnect industry. While the number of
testing options for plated through hole thermal cycling has increased,there has been little work performed within the industry
on developing methods to analyze and use the data coming from these new test methods.
This paper covers use of IST testing to obtain plated through hole cycle to failure data followed by methods to analyze and
plot the data over a wide range of temperatures. In particular,the paper will focus on the use of material properties like the
modulus as a function of temperature and the coefficient of thermal expansion as a function of temperature to calculate the
stress on a plated through hole versus temperature. In this paper we will also explore the use of the Inverse Power Law (IPL)
to analyze the plated through hole stress versus cycle to failure relationship. Once we have used IPL to established the cycle
to failure relationship to stress for a given laminate and PCB design,it is then possible to estimate the number of cycles to
failure in the field as a function of the number of cycles of assembly stress,the peak assembly temperature,and the maximum
temperature in the field.

Volume electronic manufacturing environments are constantly seeking solutions to bottlenecks at end-of-line test.
Bottlenecks are being seen increasingly on high volume automotive,telecomm & consumer electronic product lines where
assembly beat rates are much faster than that of the test processes. Manufacturing engineering teams have few available
solutions that can maintain test coverage and not increase the unit cost of test. Until recently the only viable solution required
replicating the test platforms to gain more capacity to deal with the higher volume demand. This solution consumed more
floor space,capital budget,operators & maintenance time. New solutions using concurrent test techniques promise to unblock
the test bottleneck by maximizing the test platform asset utilization across multiple units under test simultaneously.
Electronics evolutions and revolutions – whether in component technology or in the products in which they are used –
continue across the globe. While the world awaits the next electronic must-have marvel like the PC or the cell phone,the
evolution and continual re-engineering of existing consumer,commercial and aerospace products is as fast-paced as ever.
Electronics manufacturers continue their quest for products that provide greater functionality and consume less power,
typically in packaging that gets smaller and smaller.
As a result of this continual evolution,new technologies and trends in the production of printed circuit boards are required,
presenting new challenges for how PCBs are built and tested.

Selecting an optimal test strategy is a complex task today. There are many test inspection and test methods available. The
most common choices to find manufacturing defects on printed circuit boards are manual visual inspection (MVI),solder
paste inspection (SPI),automatic optical inspection (AOI),automatic x-ray inspection (AXI),in-circuit test (ICT),and
functional test (FT). This paper presents the key attributes to consider when designing a test strategy selection tool and how
such a tool should work. Among the key attributes when selecting an optimal test strategy are: defect spectrum and defect
levels,where in the manufacturing process defects are introduced,different test and inspection systems’ test effectiveness,
cost of test and inspection systems including programming and fixturing,cost of finding defects at different stages in the
manufacturing process or in the field,and of course the complexity of the printed circuit board. Outputs from the tool should
include yield calculations,DPMO (Defects Per Million Opportunities) at different stages of the manufacturing process,cost
impacts,and defects captured and defects escaping. These predictions should be made for the different test strategies
selected for analysis. The paper will describe how such a Test Strategy Tool can be design and also results in using a tool
described in the paper.