Lower cost is frequently listed as the main driver for moving to embedded passives. Unfortunately,understanding
the true cost difference between a design using embedded passives and the same design using discrete passives is
complicated. These discrepancies span design,board fabrication,materials,and assembly. While a variety of factors
influence the cost difference,one of the major cost drivers involves layer count and board size. Designs with
embedded passives often fit on smaller boards when compared to designs with discrete passives. However,although
the cost per square inch of the embedded passives board is higher than the discrete alternative,the total cost of the
smaller board may be less.
This paper analyzes drivers that influence the design size and layer count. A methodology is presented for
accurately predicting the final size and cost of designs with embedded passives as well as with discrete passives.
This methodology includes design routing analysis,escape routing analysis for BGA’s,board surface area analysis,
and panelization details. The cost impact of these size differences is also analyzed using activity based cost models
for board fabrication and assembly.

This paper presents an emerging technology for embedding discrete ceramic thick-film capacitors directly into
printed circuit boards. Their use frees up surface real estate allowing for smaller boards and/or for more silicon on
the board. They also lower inductance,impedance and radiated emissions. Previously,the technology has been
limited due to lack of component values,performance and availability of commercial materials. These issues,
however,are being eliminated and CTF embedded passives are emerging as a feasible technology. The CTF
capacitor materials are robust,and discrete capacitors can be designed to a wide range of values and physical shapes.
Materials,processes and design guidelines and manufacturing tolerances are discussed. Drivers are performance,
miniaturization,and cost.

Successive generations of ICs demand higher peak current levels and faster current rise times,challenging traditional surface
mount decoupling. The considerably lower parasitic inductance of integrated capacitors and the structures associated with
them are an enabling technology to prevent decoupling from becoming a system limitation. In addition to better electrical
performance,integrated capacitors eliminate the solder joints that must be placed at the hottest part of the board,improving a
significant reliability issue,and free up real estate near the chip for other uses.

Embedded passives are entering a new phase of improved product capability and enhanced processes. Thinner,
higher capacitance embedded distributed capacitance (EDC) materials are coming to market. Alternate resistor
forming and trimming technologies have recently been released,and discrete embedded capacitor technology is
emerging. This paper will focus on embedded distributed capacitance and embedded resistor technology,with a
brief discussion on embedded discrete capacitors and supporting technology.

This paper will highlight the shortcomings of each of the commonly used surface finishes available on the market
today. The goal is to spark the industry interest,that it may double its efforts in resolving the technical issues
surrounding the existing processes and to develop emerging products.
This discussion will be from the OEM’s point of view,as well as concerns from the Fab and Assembly side of the
equation. Finally,the paper will also discuss the industry needs going forward; especially regarding the tight pitch
tendencies and higher speed requirements of future systems.

The development of two new industry specifications – IPC-4553 (immersion silver IAg) and IPC-4554 (immersion tin ISn)
are well under way. Following in a tradition started with the development of the 4552 ENIG specification,it is customary for
this committee to present an update in the form of a technical paper on the progress of any specification under development.
The acceptance and subsequent release of any technical specification should be based on the data generated to justify it. This
committee prides itself on data generation being the backbone for any specification that it works on. This technical report
outlines the data generated to date,for both immersion silver (4553) and immersion tin (4554) deposits. Some of the data is
from completed tests while other data sets are ongoing.
As with the 4552 ENIG specification it is the intention of this committee to justify all parts of these two specifications
currently in progress with a completed technical paper that will be attached to the document in the form of an appendix.

Sn/Cu lead-free solder is a good alternative to 63/37 solder for use in HASL processes. Solderability of Sn/Cu
surface exceeds that of 63/37 solder,nickel-gold,OSP,silver,and immersion tin both before and after heat induced
aging.

With increased environmental legislation against lead in the electronics industry1,circuit board manufacturers are
expecting chemical suppliers to formulate lead free alternatives with the same functionality as tin/lead. These
alternatives are needed for board finishes,in the solder,and on the components adhered to the circuit board. It is a
benefit for the chemical supplier to educate the assembler and Original Equipment Manufacturer (OEM) on the
differences experienced with these new alternatives. The appearance and characteristics of these new finishes vary
somewhat from the incumbent lead-containing standards. Functionality remains the same if not better in some
cases. The main focus of this study was the immersion silver surface finish. As interest moves away from HASL
final finishes there has been a greater attraction to immersion silver in particular. This paper will explore the effects
of operating and storage environments on immersion silver surface finishes and help to explain the functional
capabilities the finish has after accelerated aging conditions.

Numerous industry studies have been performed examining the compatibility between new plating finishes and other metals
used in printed wiring assemblies. The transition to the new printed wiring board finishes has been driven by global lead-free
legislation and a desire for more coplanar surfaces. The most commonly examined metals have been immersion finishes,
such as immersion silver,immersion tin,and electroless nickel / immersion gold (ENIG). The industry studies have
demonstrated the producibility,testability,and reliability of these three immersion finishes; however,very little investigative
data can be found concerning the galvanic compatibility between these finishes and other metals used for structural
interconnects (e.g. aluminum). This paper documents a galvanic compatibility examination between these three common
finishes and aluminum,using both temperature/humidity and salt spray test environments with an applied electrical potential.
The test results illustrate that these three immersion finishes are galvanically compatible with aluminum when best practice
material considerations are applied.

Traditionally,the evolution of advanced IC assemblies has been due to defense and aerospace applications,where
reliability,size and weight were at a premium,and cost was a secondary consideration. In the 1980’s,high
performance computing became the advanced packaging development stimulus. That world changed again in the
late 1990’s with the emergence of ubiquitous digital content,providing impetus to the consumer markets of digital
cameras,cellular phones,portable computers,PDAs and other similar high volume applications; these have now
become the “driver” for advanced assemblies of semiconductors. Assemblers of state of the art consumer products
are developing sophisticated packaging and interconnect approaches that more and more rely on the use of die
products for these types of applications. Die products are defined as bare die,bumped die or “wafer level packaged
die” that change the overall “footprint” on the mounting substrate when the die size changes. This paper reviews
several of the die products technologies,and outlines mounting challenges to their use.