Interest in the adhesive strength of PCBs has recently come to the forefront of the industry. This has been driven by the
advent of lead free soldering processes that severely stress the mechanical properties of the board. For sometime,the
accepted test method for measuring adhesion in the PCB industry has been the widely used peel strength test. At the same
time,it has been common knowledge within the industry that this technique has been less than adequate in guarding against
delamination failures during reflow and wave soldering. In recognition of this deficiency,a new test was recently introduced
and the test method is now a part of IPC 650; the so called “T260 Method” in which a thermal event is imposed that causes a
delamination of the test specimen.
This paper presents a statistical comparison of the two test methods. The correlation is found to be very poor indicating the
failure mechanisms measured by the two tests are structurally dissimilar. An analysis is then carried out to mathematically
define the stress fields created by the two tests. As suspected,the stress fields are significantly different. Finally,these two
tests are used to compare the strength of two different copper adhesion promotion chemistries,the Black Oxide coating and
an Alternative coating. Most empirical observations have found that the performance of the coatings is equivalent; however,
only the T260 test agrees with this observation.

The emerging technology known as ‘flipchips’ is poised to take over the world of the portable device. In an age when
more and more power and functionality is being offered in ever smaller packages,the flipchip will become mainstream in
delivering the promise of “Information at Your Fingertips,Anytime,Anywhere”.
Flipchip technology places a specially prepared silicon chip onto a substrate for connection to other chips and to the
outside world. Also known as Direct Chip Attach,it uses no traditional packaging,no bond wires,has no lead frame,and
has a number of significant advantages and disadvantages compared to current mainstream technology.

New Chip Packages for advanced electronics are striving for higher density of the printed wiring boards. However,in the
supply chain,the PWB fabricator is often the last link that will learn what is needed in terms of packaging density,hole size,
line width and space,surface finish and dielectric material requirements.
At the Wireless Terminal Business Unit of Texas Instruments in Denmark,new packaging technology combined with new
chip functions are tested in reference designs. This takes place one to three years before the products enter the market in
larger quantities. At the early product development only small number of PWBs have to be made to prove that the
functionality of the hardware is working and to provide software engineers with "Reference Design" printed circuit boards
that will enable software engineers to develop the software for new mobile phone applications.
PWB fabricators that are involved in the early product development have to manufacture PWBs using new fabrication
technologies and often new materials as well. The involvement in this advanced technology allows the PWB fabricators to
have a one to two years time span to get the technologies and materials integrated in production for large quantities. The
reality often demonstrates that proto series are made at companies that do not manufacture volume series at a later stage.
Making fast turn around in small series block relatively high capacity in a volume factory and is often avoided unless volume
orders are attached.
Based on the past history,it will be explained how difficult it was to have the total supply chain lined up to meet the PWB
fabrication technology to manufacturing PWBs for latest chip packages and to be able to source high quality PWBs at
acceptable delivery time and cost.

Fluctuating demand for electronic equipment has led to repetitive “boom and bust” business cycles throughout the electronics
“food chain.” Double ordering,inventory building and component outages in expansionary times are followed by
recessionary periods where demand shrinks,excess inventory must be consumed and severe downward pricing and margin
pressures are the norm. Raw material and process equipment suppliers see amplified demand in growth periods and severe
draughts during recessions because of inventory building and reductions at each level of the supply chain.
This paper compares the relative growth (and time shifts) at each level of the supply chain at various periods in the business
cycle. Items studied include:
- Economic indicators
- Electronic equipment orders,shipments and inventories by end market
- Semiconductors
- Connectors
- Printed circuit boards
- EMS demand
- Process consumables and equipment used to manufacture and test “members” of the electronics food chain.
Global and N. American data sources are identified and utilized including process consumables from the IPC statistical
surveys.
These data sources can be used to understand and predict the timing and magnitude of forthcoming downturns and recoveries
in the electronic industry business cycle. The methodology discussed applies to the entire “food chain” – electronic
equipment manufacturers,EMS companies,PCB and other component manufacturers and suppliers of materials and
equipment to these companies.

Information Technology has come a long way from the humble payroll accounting system to integrated suite of business
applications,ostensibly to assist corporations to manage their businesses more effectively. IT disciplines in some
corporations even have a Chief Information Officer at the executive VP level with considerable clout and influence in
orchestrating the pervasiveness of IT at the all levels of the corporation. This has fueled a great appetite of expectations from
major system houses to develop and deploy the IT/ information thinking notably at the middle and top level of management.
There is ample evidence that moneys and efforts have been deployed,however the results are mixed. This paper discusses the
challenge of deploying IT and systems thinking in the corporate suite: a collection of tactical and strategic information
displayed about the performance of the business not very different from the information displayed to a driver in the
dashboard of an automobile.

As PCB computing bus frequencies climb above 1GHz,measurement of the high-frequency properties of PCB materials
becomes critical for design modeling. Understanding these properties and their dependence on temperature and humidity will
enable manufacturers to formulate new materials that will be less subject to variation. This paper will introduce a method of
measurement of loss tangent and relative permittivity of solder mask from 1.2 to 10.2 GHz and show the sensitivity of these
properties to variability of temperature and humidity. The solder mask is coated on one side of a Corning® 7980 high-purity
fused silica (HPFS) disc. This disc is inserted in a split-post dielectric resonator (SPDR). The resonance of the SPDR plus
uncoated disc is compared to the resonance of the SPDR plus coated disc to calculate the loss tangent and relative
permittivity of solder mask. This coated-disc technique has been used to determine the properties of other microwave
materials.

The trend towards tighter pitch,smaller features,and shrinking pad sizes have put a strain on the standard photolithographic
processes for soldermask patterning on substrate packaging and rigid Printed Circuit Boards (PCB). These constraints have
limited the ability of the package/board designer to shrink features and have resulted in yield losses by the fabricators. To date,
the answer to this situation has been to re-capitalize with expensive Laser Direct Imaging (LDI) systems or modified
semiconductor step and repeat equipment. This paper discusses direct laser ablation of soldermask as an alternative technology
to enable fabricators to achieve very tight soldermask feature control.
Presented in this paper is the process and performance evaluation of the direct laser ablation process on soldermask for very fine
pitch package placement on printed circuit boards. Results of solder adhesion,pre-surface finish pad morphology,and solder
joint reliability to shock,bend,and thermal cycling are reviewed across design and process parameters. The evaluation looked
at fabrication process variations across different soldermask types and soldermask thicknesses. Design implications between
soldermask defined pads,metal defined pads and via in pad when used with soldermask direct laser ablation were also
investigated.

Polymer-ceramic nanocomposites based on new concepts were developed for embedded capacitor applications. The dielectric
constant was above 80 at 1 MHz and the specific capacitance was successfully achieved 8 nF/cm2. By use of this
nanocomposites,multilayer printed wiring boards with embedded passive components were fabricated for prototypes. The
following technologies would be reported in this conference.
Firstly,based on the investigation of barium titanate (BaTiO3) crystallites,various particles with the sizes from 17 nm to 100
nm were prepared by the 2-step thermal decomposition method from barium titanyl oxalate (BaTiO(C2O4)2 4H2O). It was
clarified that BaTiO3 particles with a size of around 70 nm exhibited a maximum dielectric constant of over 15,000.
Secondary,the BaTiO3 surface modification based on a new concept was applied to improve the affinity between BaTiO3
particles and polymer matrix. Thirdly,the blend polymer of an aromatic polyamide (PA) and an aromatic bismaleimide (BMI)
was employed as the matrix from a view-point of both the processabilty during fabricating the substrates with embedded
passive components and the thermal stability during assembling LSI chips. Finally,these technologies were combined and
optimized for embedded capacitor materials.

Nanotechnology is receiving a lot of attention from companies,universities and governments. The US $3.8million National
Nanotechnology Initiative is matched by initiatives in Europe and Asia. But what does it mean for existing businesses and
new businesses in the electronics market. Is it a real tool for today or are the applications way out in the future? Will it be
economic or outrageously costly?
In reality,nanotechnology is like a toolkit for the electronics industry; it gives us tools that allow us to make nanomaterials
with special properties modified by ultra-fine particle size,crystallinity,structure or surfaces. These will become
commercially important when they give a cost and performance advantage over existing products or allow us to create new
products.
The presentation will outline areas in nanotechnology with specific impact on semiconductors,passive components,display
materials,packaging and interconnection.

Design for test rules (DFT) for in circuit test (ICT) test pads are well known and have served the industry well for nearly two
decades. However,increasing PCB densities continually put pressure on board designers to eliminate ICT testpads.
Furthermore,recent technical advances in operational board speeds are leading some designers to believe that ICT test pads
cannot be added in the high-speed sectors of boards soon to be designed. Since the effectiveness of ICT is directly related to
test pad access,some have questioned the long-term viability of ICT in this high density/high speed PCB environment.
Parker has introduced a new ICT probe technique in 2004 to address these issues.1 We’ve been calling them “bead probes”.
Parker shows that this new technique will not degrade the high-speed circuit performance of tomorrow’s gigabit logic boards.
He also presents test results showing that this new technique can be used with typical PCB assembly processes and ICT
fixtures with similar electrical performance and reliability to current ICT probing techniques.
This paper will continue that discussion and further demonstrate how these non-traditional pads have little impact on layout
for test pad placement using results from a real PCB design process. It will discuss DFT guidelines for “bead probes” and
discuss possible barriers to creating beads in an outsourced manufacturing environment. Finally,now that ICT access to highspeed
sectors on PCBs will be available,a survey of viable ICT test techniques will be presented.