It has been demonstrated it is possible to combine design, process, and metrology information to create machine learning models that accurately predict the behavior of individual products in the manufacturing line. In this work, we extend the application of these single process models to a full production sequence. Instead of training a large machine learning model to describe the full production sequence, we sequentially train the models in a way that prior models can be used to impute the sparse manufacturing data of previous process steps. This approach uses process and context-aware methods to effectively augment real-world facility data that is otherwise expensive to collect. By doing so, it is possible to identify which process steps have the most impact. While the primary work was validated in the final electrical test after a Back-End-Of-Line process, the methods used have been demonstrated to work in packaging operations. Two of the challenges to apply machine learning methods to manufacturing processes, are the complexity and heterogeneous nature of each individual unit operation, as well as the lack of complete characterization for every single item being produced due to throughput and cost constraints. In this work we demonstrate the benefits of using a hierarchical approach to product manufacturing in which individual unit operations are modelled individually, but results of previous operations inform and forecast subsequent manufacturing processes. To demonstrate this methodology, we have selected a portion of a Semiconductor manufacturing process, composed by over 40 distinct unit operations.

Additive manufacturing (AM) methods to fabricate and repair printed hybrid electronic (PHE) components and interconnect systems create compelling opportunities in 3D curvilinear architectures for printing RF components and interconnections. However, significant technical challenges remain that must be overcome to develop practical techniques for assuring consistently reliable outcomes. Some of the important RF technology applications where new process development efforts are needed for successful deployment of additive manufacturing methods are: PIN Diodes (die encapsulation and conductive ink interconnections); Coupling Transformers (printed core and windings); and Direct-write Interconnect-over-Fillet (IoF) architecture for mmW MIS Capacitors. When fabricating high-performance RF circuitry for performance up to 40 GHz, direct-write printed versions have the potential to provide a distinct advantage over traditional components by offering smaller form factors and unique conductor/dielectric material formulations. the robustness and reliability of such printed structures have not been sufficiently investigated and demonstrated. The objective of this presentation is to highlight the results of the multi-year effort to develop and environmentally test (temperature excursions, static and dynamic mechanical stresses, and humidity) the RF technologies listed above.

Lower temperature soldering has been regarded as one of the most effective ways to reduce warpage risk. Use of lower-temperature solders, including a BiSnAgCu eutectic and two In-containing, Bi-free solders - ILT, and ILT-2 has been attempted to reflow the 40 mm x 40 mm plastic ball grid array (PBGA928). BiSnAg, under the combinations of reflow profiles P185 and P200 (~185°C and ~200°C peak temperature) and the paste-to-ball (P2B) volume ratio (0.13, 0.25, and 0.5), always formed defective joints. Under the P200 profile with P2B volume ratio of 0.5, SAC305/BiSnAg joints were still dominated by defects, including hot-tearing and shrinkage voids despite forming the desired drum shape. With the constant 0.13 P2B volume ratio, P200 also renders various malformed joints for both ILT and ILT-2. Increasing reflow temperature improved the joint shape and greatly reduced the defects for both ILT and ILT-2. In P220, both SAC/ILT and SAC/ILT-2 joints achieved the desired short-and-fat drum shape, comparable to those reflowed under P240. The formation of the optimal joint is attributed to the sufficient liquid solder volume since both paste and SAC ball melt and merge under the hot profiles, which compensates the displacement caused by the dynamic warpage. Both SAC/ILT and SAC/ILT-2 joints only exhibited limited hot-tearing under the P200 profile. The different metallurgy of ILT and ILT-2 did not result in an enlarged pasty range after joining with SAC305 and thus led to the lower defect rate. Investigation of the joint reliability performance is still ongoing.

Gallium-based liquid metals have remarkable properties: melting points below room temperature, wide conductivity, water-like viscosity, low toxicity, and effectively zero vapor pressure (they do not evaporate). They also have the largest interfacial tension of any liquid at room temperature. Normally, small volumes of high-tension liquids form spherical or hemi-spherical structures to minimize their surface. However, due to a thin, rapidly forming oxide skin, gallium-based liquid metals can be patterned into non-spherical shapes (cones, wires, antennas, or films for thermal interfaces). In addition, the metal can be rendered into a ‘gel’ or ‘paste’ by incorporating other materials such as oxide flakes or metal particles. These additions change the rheology of the metal and thus, its flow mechanics during nozzle dispensing. This talk describes efforts in our research group to pattern and manipulate metal into useful shapes—such as circuits or thermal interface contacts—that take advantage of the properties of liquid metal. It is possible to pattern liquid metal in unique ways, such as injection or direct-write 3D printing at room temperature to form ultra-stretchable wires, self-healing circuits, and stretchable barrier materials. Perhaps the most fascinating aspect of liquid metals is the ability to use interfacial electrochemistry, removing/depositing the oxide to manipulate the surface tension of the metal over unprecedented ranges (from the largest tension of any known liquid to near-zero). This work has implications for thermal interface materials as well as soft and stretchable electronics, both being devices with desirable mechanical properties for human-machine interfacing, soft robotics, and wearable electronics

Voiding and solder coverage in SMT solder joints remain a matter of (sometimes emotional) debate in automotive electronics. Meanwhile voiding/solder coverage requirements have been introduced into IPC J-STD-001HA/IPC-A-610HA. But beside the question of reasonable requirements, the topic of void quantification in sample and mass production has to be addressed as well. Many X-ray inspection systems available on the market are offering an automated void quantification option for different solder joints. The question arises how repeatable and reproducible these void values are in a normal sample and mass production environment.
To address this question, a round robin study has been organized by a working group of the ‘Deutsche Kommission Elektrotechnik’ (DKE, the German Electrotechnical Commission) with participation of several automotive electronic stakeholders, including Tier1 suppliers, OEMs and suppliers of X-ray inspection equipment. Predefined components on six product or test boards have been analyzed by nine different evaluators. Solder joints of BGAs, QFNs (especially thermal pads) and chip-Rs have been X-rayed to cover a wide range of solder joint geometries. To investigate the repeatability, all solder joints have been analyzed 25 times.
The final evaluation shows poor repeatability of the analyses at one location, but even more pronouncedly, the reproducibility at different analysis locations was considerably worse than expected. Exemplary results of this study are presented together with main conclusions and recommendations for improvement and void control strategy in mass production. The findings also indicate that discussions about solder coverage requirements on a single-digit level are in vain.

At present, with the rapid change of the server market, Eagle Stream platform chipset, which changes the traditional practice of Whiley platform material selection and stack mode compared with the previous and provides a new reference perspective for everyone.
The Eagle Stream platform differs from the Whiley platform in the selection of materials. First, the Eagle Stream platform imposes higher requirements on materials with excellent electrical properties to meet the high frequency and high speed signal transmission requirements of the new platform. In the way of stacking, it also reflects innovation and change, choosing a more complex, but more efficient way to improve the overall performance.
The insertion loss of Eagle Stream platform material is analyzed in this paper. Insertion loss is an important electrical performance indicator, which can reflect the degree of influence of electronic devices on signal transmission under certain conditions. Through a large number of experimental data, we found that the insertion loss of the same material under different structures is significantly different, even enough to affect the overall electrical properties. Therefore, when selecting materials, we should not only pay attention to the performance of the material itself, but also consider its stacking mode in practical applications.
This study provides a direct and effective reference for the material selection of Eagle Stream platform, which is of great significance for optimizing product performance and improving product competitiveness. In addition, we also look forward to the emergence of more innovative platforms after the Eagle Stream platform, which can further promote the development of the server market and better meet user needs.
Keywords: Eagle Stream platform, Insertion loss

The 4-14F IPC Standards Committee are close to finalizing (at the time of writing) a revision to the IPC 4556 specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) finished Printed Circuit Boards (PCB). Revision A brings a more comprehensive evaluation of metal layer thickness measurements, compositions, and introduces a quality aspect for nickel corrosion following a successful publication of the revised IPC-4552B (ENIG specification).
The introduction of these revisions will ensure a higher level of quality for conforming ENEPIG deposits, but it will also present some challenges in achieving and consistently delivering the required level of quality from PCB fabrication.
IPC-4556A will require the PCB fabricator to demonstrate capability in measuring and maintaining electroless nickel, palladium and gold thicknesses, electroless nickel %P composition along with conformance to a newly introduced corrosion specification. IPC-4556A covers traditional ENEPIG using immersion gold technology and introduces a newer gold plating technology – reduction assisted gold (also known as hybrid or semi-autocatalytic gold). In short, the fabricator has more work to ensure an IPC-4556A compliant ENEPIG deposit.
This paper will provide a comprehensive review of IPC-4556A, supplying explanations and examples of conforming and nonconforming ENEPIG to help the fabricator understand and embrace the challenges posed by the new specification and provide a higher quality ENEPIG deposit.
Key words: IPC-4556A, ENEPIG, electroless nickel, electroless palladium, immersion gold, hybrid gold, reduction assisted immersion gold, semi-autocatalytic gold corrosion.

Continued microelectronic miniaturization has resulted in higher power density, increasing the need for high performance thermal management. One solution for board-level thermal management is to encapsulate a high thermal conductivity material, such as pyrolytic graphite (~1700 W/mK) in a metal (such as 6061 aluminum alloy), producing an efficient passive heat spreader for thermal dissipation. The metal shell provides mechanical strength at a small detriment to the overall thermal conductivity. Reliability and consistent performance over time are critical for thermal management systems, especially in Defense and Aerospace applications. MIL-STD-883H provides test parameters for reliability involving exposure to mechanical shock (Method 2002.5), mechanical vibration (Method 2005.2), and thermal shock (Method 1011.9), with traditional evaluation criteria involving microelectronic device performance and/or a visual examination. For this work, the reliability of aluminum encapsulated graphite test coupons was evaluated with more demanding criteria: a visual examination, X-ray inspection, acoustic microscopy, and thermal conductivity performance testing, both before and after the previously discussed MIL-STD-883H exposures. The encapsulated coupons showed excellent robustness; the thermal conductivity properties remained constant with an average value around 965 W/mK, and the non-destructive imaging revealed excellent bond quality with no evidence of delamination. This more stringent evaluation criteria after MIL-STD-883H testing can evaluate the reliability of passive thermal management systems. The study results demonstrate the metal encapsulated graphite heat spreader as a superior thermal management solution, enabling greater power dissipation than typical aluminum and copper heat sinks and demonstrating high reliability surpassing that of industry standard testing.

In advanced printed circuit board and IC substrate production, the metallization for blind vias and through vias (also called through holes – TH) is essential for the build-up of the PCB or IC Substrate. Filling of vias is important for planarity of the PCB as next mounted layers or components need to be placed with tight tolerance. It also helps to prevent moisture ingress, which can lead to corrosion and electrical issues over time. Filling of through vias with metallic copper by electrolytic plating provides various advantages compared to plugging paste, such as higher electrical and thermal conductivity as well as higher reliability, better mechanical stability, and reduced number of process steps. First through via filling process was described in 2005 [1], but also other emerging technologies, like the replacement of organic materials with glass for the core layer of IC Substrates, would benefit from advanced through via filling processes. Today, through via filling is primarily done in two different types of equipment, namely copper plater with horizontal transportation of the panel and vertical conveyorized plating (VCP) equipment.
Challenges that the industry is facing are driven by PCB and IC Substrate designs that require void-free filling of high aspect ratio [2] structures coupled with overall increasing number of through vias on a panel with areas of high hole density and areas with low hole density. In addition, based on circuitry density, pattern plating might be required.
In order to fulfill the demanding industry requirements, it is important to understand the interplay of chemical (electrolyte) and physical (equipment, process) parameters by identifying key factors influencing the mechanism of the through via filling process. In this paper we will review current state of the art of through via filling with electrolytic copper deposition from established horizontal plating systems [3] to newly developed pattern through via filling in VCP equipment with pulse plating. One example for a filled through via in pattern mode is shown in Figure 1.

In HDI (high density interconnect) PCB (printed circuit board) and IC Substrate (integrated circuit substrate), a successfully formed and plated laser via is crucial to the overall system and/or package functionality, as well as for the product’s reliability. Simultaneously, total via density per unit is increasing, driven by demands for higher feature quantities and enabled through new miniaturization technology in board (substrate and PCB) manufacturing processes and equipment. Hence, the importance of an optimized via formation process takes center stage for the current and next waves of technology development.
Thus far, a board manufacturer’s key process support for via formation has largely come from singular supply chain partners; e.g. via drilling support from one supplier, desmear support from another, plating support perhaps from yet another. While top board manufacturers demonstrate skillful expertise in the total process landscape, new challenges require specific technological development from such key suppliers. And yet, cooperation between process equipment and chemistry suppliers remains punctuated at best, for various reasons, which may limit absolute leverage for true solution finding.
A comprehensive, total via formation process landscape ownership would carry with it many benefits that would otherwise remain unexplored. We’ll focus on what such a single-source via formation development could look like, while simultaneously looking at some new system technology. A holistic via formation approach (pretreatment, via drilling, desmear, electroless/galvanic plating) may support the optimization the interconnect and new advances in form, function and reliability.