Deep microporous crab legs and abnormal crystallization of coating are common defects in the electroplating process, which have a significant impact on the reliability of PCB products. In this paper, the finite element analysis method is used to numerically calculate the flow state of the plating solution on the PCB surface and in the hole during the jet process. The velocity distribution of the plating solution in the blind hole with different aspect ratio (AR) was obtained. In addition, the influence of electroplating parameters such as current density, waveform time ratio, positive and negative current ratio on the effect of deep microporous electroplating is studied through experiments. The results show that when electroplating and jet flow parameters are synergistic, these defects can be effectively improved.

Chiplet technology is rapidly applied to the latest devices as high performance of semiconductor devices is required. As chiplet becomes vibrant, IC packaging substrates become bigger and more layered. High current density is required due to these changes of IC packaging substrates.
Wiring design also becomes complicated as the technology is matured. Especially IC packaging substrates have various wiring in a board such as L/S 8/8 μm below dense line pattern and 20 μm isolated line pattern.
Dense line pattern mentioned above is likely to have thinner plating deposition as electrical current flow is dispersed. On the other hand, isolated line pattern is likely to have thicker plating deposition as current flow is concentrated. Therefore, it leads to plating thickness unevenness.
Current density gap between isolated and dense fine line pattern is relieved by increasing electric charge of Nitrogen type organic compound (Leveler), and it leads to superior plating thickness uniformity.

Applications for dielectric materials are becoming ever more demanding and complex, requiring careful planning & material selection by original equipment manufacturer (OEM) designers that wish to build reliable products. Some applications may be purely digital and benefit from a very low dielectric constant (e.g., Dk < 3.0) while others, such as radio frequency (RF) applications with high power requirements may benefit from having a higher Dk (e.g., >5). An emerging trend now is the rise of hybrid product designs that combine both traditionally digital and RF materials, especially in the case of high-density interconnects (HDIs). In this paper, methods for tuning the material Dk by careful selection of specialty resins and filler material combinations will be reviewed. The use of mineral fillers for achieving high Dk is a well-established practice that comes with certain considerations such as safety, drilling compatibility, and effects on signal integrity. By contrast, the use of hollow fillers to achieve low Dk is a more recent development that comes with similar considerations, along with chemical composition and morphology concerns. Each of these concerns must be addressed by the product designer, and careful, reliable measurement of the Dk is critical to validating product performance.

The growing demand for high-performance and compact electronic devices has led to increasing power densities, resulting in thermal challenges that impact packaging, performance, and reliability. This paper describes controlled viscosity molding (CVM) applied heat transfer material to a printed circuit board assembly compared to heat removal of mainstream methods. Passive thermal management is chosen as a basis for comparison but is not limited in design. This paper does not include active or advanced heat transfer methods, such as heat pipes or advanced thermally conductive materials, as early developments remain focused on consumer grade technologies and serve as a more acceptable form for comparison. It is focused on demonstrating suitability as a heat transfer method while preserving electronic functionality and in some cases increasing system performance while preserving damaging temperature limits. Thermal simulations have been performed in parallel to confirm and build confidence in some baseline tests. Thermal simulations can serve as a proxy for functional prototypes saving time and money while mitigating risk to product development. A commercially available Battery Management System (BMS) is used for the basis of comparison because of its availability, cost, and use of common heat generating electrical components. CVM with heat transfer material on a printed circuit board can replace aluminum heat sinks as a passive heat control method.

Today, the evaluation of circuit board assembly materials extends beyond their technical performance. An increasingly important aspect of this evaluation centers on whether the material helps improve the sustainability of the organization. The assessment of assembly materials for circuit boards now encompasses their environmental impact across raw material sourcing, industrial processing, and end-of-life management, as well as their societal implications for the well-being of manufacturing personnel and end-users, all while considering cost-effectiveness. It is the responsibility of material suppliers to deliver innovative solutions that meet these multifaceted criteria. This paper delves into circuit board assembly materials, spanning from low temperature solders and reinforcement polymers to bio-based encapsulation resins, with a primary focus on sustainability.

Polycarbonate/Acrylonitrile butadiene styrene (PC/ABS) blends are widely used engineering thermoplastic materials in electronic applications for TV frames, computer peripherals, phone housings/cases, device enclosures, etc. While PC/ABS blends are generally tough, certain chemical environments can contribute to catastrophic brittle failure at relatively low stress levels. Global concern on e-waste and growing emphasis on sustainability lead to increasing adoption of Post-Consumer Recycled (PCR) plastic resins in the production of consumer electronics, which has also increased the demand for PCR PC/ABS materials for the electronics industry. However, high loadings of recycled content may trade off mechanical integrity of the materials, making the blends more susceptible to Environmental Stress Cracking (ESC) and fatigue related part failures. Novel PCR PC/ABS blends using tailored polycarbonate siloxane copolymer chemistry show significantly improved stress cracking resistance. They support very high loading of recycled components (60-80% PCR PC, and up to 86% renewable content) while maintaining excellent chemical resistance to consumer chemicals, such as sunscreen, skin oils, and insect repellent. They also deliver high impact resistance across a wide temperature range (down to -30 oC) that traditional flame retardant (FR) PC/ABS materials do not possess. Furthermore, the new PCR PC/ABS blends offer comparable FR performance, heat resistance, modulus/strength, flow characteristics, and color-ability to traditional blends. This paper will also review various ESC testing methods and compare new PCR PC/ABS blends with other PC based blends.

Thermal-aging induced crack formation of fiber-reinforced polymer composites in printed circuit boards (PCBs) is a major failure mode affecting the reliability of electronic control units as temperature requirements increase. In this study first findings on the degradation behavior of PCBs are presented. Thermal stress accelerates oxidation, ultimately leading to degradation of the material, characterized by the occurrence of cracks in near-surface regions. The oxidation of the material is shown by Fourier transform infrared spectroscopy (FTIR). The crack occurrence depends significantly on the oxidation layer thickness. By means of dye penetration, scanning electron microscopy (SEM) and focused ion beam (FIB), the microscopic structure of the crack is revealed. Finally, a hypothesis on the degradation mechanism is deduced.

As the data rate is getting faster with the development of applications such as High Performance Computing (HPC), Data Center, and Artificial Intelligence (AI), it is found via stubs are affecting the signal quality on those server Printed Circuit Boards (PCBs). The back drill process has been adopted to mitigate the via stub effect, but there can be skewed drilling which causes via stub residue in manufacturing of the PCBs. Therefore, using a impedance measurement technique by time domain reflectometry (TDR) to confirm the quality of via back drilling may be necessary. However, the resolution of the TDR instrument for via stub inspection is affected by the quality of channel and accessories. How to ensure the quality of the system before measurement is very important. Three approaches were proposed to achieve the robust and accurate measurement process. In the beginning of the experiment, a transmission line with via stub effect was designed as the device under test (DUT). It was sent to the Taiwan Accreditation Foundation (TAF) testing laboratory to obtain a reference value. The reference value includes minimum via impedance and main routing impedance. The next step is to use one-way analysis of variance (ANOVA), to investigate the impact of different contact impedance and probe skew on via impedance and main routing impedance. In the final step, linear regression is used to evaluate probe quality assurance for the robust and accurate measurement, which means probes with less effect to via impedance. Linear regression method is used to evaluate the impact rate for probes quality selection. If the impact rate is less than 5 %, the contact impedance and skew of probe characterization is less than 4.5 ohms and 45ps, respectively. Another characterization approach is the use of vector network analyzer (VNA) for TDR impedance measurements. A VNA with a higher frequency has a faster rise time and a better resolution length. In addition, VNA also has correction technology to mitigate the error of the system path, such as RF cable and probe.

Solder voids affect the thermal and electrical properties of solder joints, reducing their reliability. The main test for solder voids is non-destructive testing using X-ray transmission images. However, since X-ray images contain noise, it is difficult to automatically extract voids through image processing such as thresholding, and the inspection automation has not progressed. Additionally, IPC-J-STD-001HA/IPC-A-610HA defines quality standards for solder coverage, which should be able to be automatically inspected for various types of components and solder joint types. Therefore, in this study, we verified the methods for automatically measuring solder void ratio and solder coverage using multi-class segmentation technology using deep neural networks. We created a unique dataset of 1,200 X-ray images covering the components and mounting types in the IPC standards, and we thoroughly evaluated the performance of the methods. By training DeepLabv3++ on the 960 training images, it achieved 0.9752 of IoU and 0.9874 of Fscore for the 120 test images. This method was superior to the methods using thresholding processing and the other methods using deep neural networks. Furthermore, it was found that the solder coverage automatically measured using this method had a maximum error of only about 3% compared to the manually measured results. These results suggest that it is possible to accurately and automatically check whether the solder coverage of various components and mounting types meets the IPC standards not only by sampling inspection but also by in-line inspection.

Solder resist (SR) is applied to the outermost layer of printed circuit boards (PCBs) for surface protection and electrical insulation. It is crucial for the reliability of PCBs to ensure robust adhesion between SR and Cu. Current PCB manufacturing employs techniques that chemically induce micro-controlled roughness on the Cu surface, considering factors such as the surface roughness of Cu, the resin content of SR, and the type of filler. Even though heat exposure is known to deteriorate SR/Cu adhesion, the response of the SR and Cu interface to thermal aging remains elusive. In this study, a series of quantitative measurements and morphological analyses were performed to reveal how thermal aging affects the interface between SR and Cu. The growth of Cu oxide during thermal aging leads to the development of a gap between the Cu and Cu oxide layers, making the SR/Cu interfaces vulnerable to delamination. The gap formation between Cu and Cu oxide can be attributed to Cu diffusion-induced Kirkendall voids, as well as differences in crystal lattice, volume, and coefficient of thermal expansion between Cu and Cu oxide.