Heterogeneous integration has become one of the most important approaches in the semiconductor technology world. The process nodes are constantly shrinking from 16nm to 5nm and lower, with CMOS component speeds continuously increasing. This is equivalent to integrating twice the number of components in the same amount of space every 18-24 months.

CoW (Chip on Wafer) is the next generation of CoS (Chip on Substrate) that first combines the chips to the interposer, adds wafer-level molding, and finally, they are connected to the flip chip (FC) substrate. This technology makes a better physical structure for accommodating very large die and larger overall interposer dimensions.

At Apex 2022, a technical paper titled ‘Defluxing of Copper Pillar Bumped Flip Chips’ was presented. This comparative study confirmed that compared to low concentration alkaline cleaning agents, the De-ionized water inline cleaning system is challenged to consistently and effectively clean flux residues underneath low standoff components under copper pillar packages with 150μm pitch and a 30μm Cu pillar height.

This study is the continuation of the initial effort but now focuses on cleaning under the next level of ultra-fine pitch CoW devices down to less than 25μm bump pitch and bump counts more than 150K. The authors followed the test protocol utilizing the same low-concentration alkaline cleaning agent used in the initial study. In addition, the study also focuses on the impact of wash temperatures and conveyor belt speed. T

he cleaning assessment methodologies employed analytical/functional testing, including Visual Inspection, FTIR with color mapping, and SEM/EDX.

The use of modern laser systems for depaneling printed circuit boards can present many advantages as well as some challenges for the production engineer compared to conventional mechanical singulation methods. It is particularly important to properly understand the effects of the laser energy to the substrate material in order to take advantage of the technology without creating unintended side effects. The temperature response of the substrate is of central importance for many factors such as the distance of components from the cutting channel or the degree of carbonization. This paper presents an in-depth analysis of the temperature behavior of FR4 material for different laser powers and wavelengths. The temperature measurement was carried out by using Type-K thermocouples applicated in non-plated through holes. These have been positioned at distances with a regular interval to the cutting channel. Thereby the temperature was measured three times for each distance during the ablation process. The result is information on the heat input in 100 µm steps distance from the cutting contour during the laser ablation process through copper layers and PCB base material. Based on the regular measurements, a temperature behavior model can be derived from the data using statistical methods. This paper is examining if the temperatures of all systems measured are considerably below the melting points of tin/silver/copper alloy, even at the smallest intervals. In addition, the authors are investigating the possible correlation between different laser wavelengths, pulse durations, laser power and cutting strategies and its impact on temperature level measured on the substrate material.

Increasing demands on printed circuit boards require new production methods. For years, lasers were mainly used for application with the highest accuracy requirements. Today, laser depaneling became more widely used since the demand for excellent cutting quality, especially for high-end applications (e.g. 5G, IoT), and increasing cost pressure require one to reevaluate the use of traditional production methods. These days lasers offer only benefits over traditional processes. In this paper, the most important facts about process quality and economic advantages are discussed. This paper analyses latest results of quality assessments and shows how laser cutting enables failure-free processes. Dust free cutting and uncontaminated surrounding PCB surfaces with highest technical cleanliness improves the durability of electronics. In the back-end of SMT lines, modern lasers enable significant cost savings with 100% stable process conditions. Several comparisons with traditional depaneling methods are described to show potential savings in PCB materials as well as cost savings in follow-up costs, post processing and efficient and fast volume scaling of production. With mathematical models about design rules and panel utilization this paper encourages PCB designers to enable economical and environmentally friendly SMT production lines.

IPC-4552 and IPC-4556 are industry performance specifications for ENIG (Electroless Nickel/Immersion Gold) and ENEPIG (Electroless Nickel/Electroless Palladium/Immersion Gold) as used for the surface finishes for printed wiring boards (PWBs). As both surface finishes are considered multifunctional in nature—solderable, wire bondable, and usable for contact switches—these performance specifications detail the many considerations for these critical surface finishes. One area of detail surrounds the acceptable coating thicknesses of the different layers of both PWB surface finishes. Much of the attention paid to ENIG and ENEPIG is focused on the precious metal layers: gold for ENIG and both gold and palladium for ENEPIG. Both documents also specify the thickness requirements for the electroless nickel layer; however, these requirements are often misunderstood. The thickness and phosphorus content of the electroless nickel layer play critical roles in the solderability, functionality, and reliability of modern electronics. Thickness measurements of electroless nickel are affected by the phosphorus content (wt.% P) in the nickel deposit. Therefore, the phosphorus content (wt.% P) in the deposit must be considered a critical variable when creating an uncertainty budget and measuring the thickness of electroless nickel.

Cupric chloride etchants are often used in PCB fabrication. They use Cu+2 to oxidize solid copper producing two Cu+ ions.[3] During operation, the etchant is overloaded with copper ions. To control concentration, an extraction system is implemented to remove excess copper. Traditional systems use liquid-liquid extractions. These systems are costly and use hazardous solvents. An electrowinning cell cannot be used because this process can release chlorine gas.[1]

A solution to this problem lies in ion-exchange resins. These resins adsorb metal ions and retain them until desorption.[2],[4] A study for effectiveness was performed using a small-scale column. Adsorption and desorption were performed with varying flow rates. Results showed that the resin effectively removes copper at various flowrates. The resin was found to remove an average of 10.06g/l Cu from a bulk volume of three beds of etchant.[1] The effectiveness is a function of the Cu concentration in the etchant and the flow rate through the resin. The relationship(s) between process time, throughput, and flow rate was investigated.

The extracted copper was desorbed from the resin using a 200g/l sulfuric acid electrolyte. The electrolyte effectively striped copper from the resin even as the copper concentration exceeded 40g/l.[1] An electrowinning cell can be used to safely remove the copper from the sulfuric acid electrolyte yielding Cu for sale or recycling. The system does not rely on liquid-liquid extraction or hazardous solvents. This is environmentally friendly as the only waste is copper plates. In contrast traditional systems produce hazardous waste when replacing the organic solvent.

In the printed circuit board (PCB) industry, the surface finish acts as both protection layer and as active enabler for a broad variety of interconnecting techniques. The deposition of gold is one of the most common processes as it is applied in Ni/Au, Ni/Pd/Au, and Pd/Au finishes. Depending on the target thickness, different types of gold electrolytes are available on the market. They differ in the plating mechanism from fully immersion reaction type to mixed reaction type gold electrolytes. In mixed reaction type gold electrolytes, the plating mechanism is as a mixture of immersion reaction and autocatalytic reaction. The reducing agent defines the portion of the autocatalytic part in this mixed reaction. To control the autocatalytic reaction, stabilizers are used which typically contain free cyanide to support the gold complexation and prevent spontaneous decomposition and plate out.

In this paper, a new gold electrolyte is introduced which exhibits autocatalytic properties to deposit high layer thickness and defect-free electroless nickel immersion gold (ENIG) deposits where the stabilizer is nontoxic and does not contain free cyanide. By this it enables an easy, safe, and stable process handling up to bath lifetimes of more than 8 g/l gold with a gold concentration of 0.5 g/l. It was tested for Ni/Au, Ni/Pd/Au, and Pd/Au deposits; the performance results were compared to the process currently applied in the industry. The evaluation focuses on the solder joint reliability of the layers, the corrosive attack to the nickel layer, the thickness distribution, and the characterization of the gold deposit.

This paper describes the novel use of Fused Filament Fabrication (FFF) 3D-printing technology to create plastic, positioning and retaining structures directly onto the surface of standard FR4 printed circuit boards (PCBs). The 3D-printed structures are retaining walls that enable the encapsulation and protection of specific, critical or sensitive components and circuits on PCB assemblies. Industries having products operating in harsh environments, e.g., Automotive, use encapsulants and other polymeric materials to provide PCB assemblies with protection from moisture and other external influences. An efficient and cost-effective solution for the protection of critical electronics components is desirable. 3D Printing allows for customization and different PCB assemblies and structures may be manipulated using the same printer. Plastic retaining walls were 3D printed onto modified, IPC-B-24 surface insulation resistance (SIR) Test PCBs as a demonstration of the technology. The materials and equipment used to print the 3D-plastic retaining walls are conventional, relatively low cost, and readily available. The FFF 3D printer, process parameters, and the FR4 PCBs required physical modification and print parameter optimization to achieve robust attachment of the printed retaining walls onto PCB substrates. The retaining walls could be printed in under two minutes, thus enabling the possibility of volume scalability. Design features were incorporated into the printed structures to reduce thermal stress. This case study describes a design, equipment, process, and materials methodological approach for the 3D printing of plastic retaining walls onto PCBs. The retaining walls assist with the encapsulation, protection, and test of critical circuits operating in harsh environments.

Direct Digital Manufacturing (DDM) combines additive and subtractive manufacturing methods to fully fabricate Printed Circuit Structures (PCS). Harnessing the flexibility of additive methods, designers may embed electronics into functional structures. This flexibility is made possible through the additive deposition of structural plastics and conductive pastes in the DDM process. For PCSs, traces are typically formed with a single layer of silver paste deposited through direct ink writing (DIW). Vias are formed by fully filling cylindrical cavities with silver pastes. However, DDM conductive features see performance far below copper and experience via yields far below that of traditional PCBs due to current manufacturing techniques and thermal limitations of the structural plastics.

A method involving stacking conductive traces was developed. This method of stacked 20µm-layers showed a 92% reduction in resistance of a trace when compared to a single-layer trace of equal height. The second method presented in this work involves coating only the walls of the via with conductive material using a novel vacuum extraction technique. Using this method, a 98 percent yield within an array of 50 printed vias has been achieved. Resistances through the via were measured to average 4mΩ. A demonstration PCS is then presented to show the impact these improvements have compared to previous DDM methods. The PCS features comparisons on trace and via resistances, and via yields, in a circuit environment representing typical additive electronics, and shows the potential for additively manufactured electronics to achieve higher levels of complexity and performance.