This paper explores the process of identifying and evaluatingpotential counterfeit parts. The military customer is aware that counterfeit parts are a problem and hascreated Defense Federal Acquisition Regulation Supplement (DFARS) 252.246-7007 to add protection and avoidance of the use of counterfeit parts in military products. Thus,defense subcontract manufacturersneed to understand and assure no counterfeit parts get into any product. This paperprovidesa real example of identifying a counterfeit part and the process taken to resolve the issue. The topics that will be addressed include:
i)Defining what,who,and how of counterfeit parts,
ii) Using an industry analysis tool to understand the counterfeit risk,
iii) Uncovering anomalous electrical behaviors,
iv) Researching the manufacturer’s part markings,
v) Informing management about the potential counterfeit part,
vi) Involving a third party to analyze and test for authenticity,
vii) Expanding the team to address the issue with the customerand distributor,and finally,
viii) Providing lessons learned and suggested future measures for avoidance.

With the dramatic increase in connected devices in the IoT era,it is becoming imperative to do much more to ensure the quality of all electronic components,especially for devices in mission-critical applications. In this paper,we will discuss actual use cases where product quality and time-to-quality was dramatically improved through the use of a seamless big data infrastructure. The data infrastructure can collect data from across the global supply chain and analyze that data in near-real-time to quickly identify manufacturing issues than can negatively impact product quality and reliability,greatly reducing test costs and downstream Return Merchandise Authorizations (RMAs). By bringing together manufacturing data from Original Equipment manufacturers (OEMs),system integrators and suppliers,overall time-to-quality for the entire supply chain can be reduced by a month or more,dramatically improving time-to-market and market share for all contributors to the supply chain.

Since the European Directives,RoHS (Restriction of Hazardous Substances) and REACH (Registration,Evaluation,Authorization and Restriction of Chemicals),entered into force in 2006-7,the number of regulated substances continues to grow. REACH adds new substances roughly twice a year,and more substances will be added to RoHS in 2019. While these open-ended regulations represent an ongoing burden for supply chain reporting,some ability to remain ahead of new substance restrictions can be achieved through full material declarations (FMD) specifically the IPC-1752A Class D Standard (the “Standard”),which was developed by the IPC-Association Connecting Electronic Industries. What is important to the supply chain is access to user-friendly,easily accessible or free,fully supported tools that allow suppliers to create and modify XML (Extensible Markup Language) files as specified in the Standard. Some tools will provide enhancements that validate required data entry and provide real-time interactive messages to facilitate the resolution of errors. In addition,validation and auto-population of substance CAS (Chemical Abstract Service) numbers,and Class D weight rollup validation ensure greater success in the acceptance of the declarations in customer systems that automate data gathering and reporting. A good tool should support importing existing IPC-1752A files for editing; this capability reduces the effort to update older declarations and greatly benefits suppliers of a family of products with similar composition. One of the problems with FMDs is the use of “wildcard” non-CAS numbers based on a declarable substance list (DSL). While the substances in different company’s lists tend to have some overlap,no two DSL’s are the same. We provide an understanding of the commonality and differences between representative DSLs,and the ability to configure how much of a non-DSL substance percent is allowed. Case studies are discussed to show how supplier compliance data,can be automatically loaded into the customer’s enterprise compliance system. Finally,we briefly discuss future enhancements and other developments like Once an Article,Always an Article (O5A) that will continue to require IPC standards and supporting tools to evolve.

The Augmented Reality and Virtual Reality market is expected to cross $44 billion by the year 2025 according to various industry experts. This exciting new technology is not exactly new,but has cutting edge potential that can change the way that we live our lives and especially how we do business. While there are many types of hardware and software out in the market,few are looking at addressing manufacturing environments. Due to the various types of “Realities” such as “Virtual Reality”,“Augmented Reality”,“Mixed Reality” and others,we will refer to any type of reality as “XR” where “X” is a variable. For this paper,we will focus only on Augmented Reality and Virtual Reality,while only mentioning some others. Virtual Reality refers to a computer-generated simulation of an environment that can be interacted within a seemingly real or physical way. Augmented Reality refers to viewing the physical environment whose elements are overlaid on top of what you are seeing live. We will discuss how both of these technologies can be used in a manufacturing environment and the key applications we have identified to use these for. In addition to the applications that we have identified,this paper will also cover the market,technology,different types of devices,software,as well as advantages and limitations that exist today

E-textiles,also known as electronic textiles,smart textiles,smart clothing,smart garments,or smart fabrics,are fabrics with electronic components and sensors embedded in them. Key components of e-textiles are the conductive materials to connect different sensors,modules and power supplies to form a body area network (BAN). In their lifetime,e-textiles including the conductive materials may experience many washing and drying laundry cycles,one of the biggest challenges facing the application of e-textiles. Limited data are available on the performance of conductive materials going through the washing and drying cycles. This paper presents studies on the washability of three types of commonly used conductive materials in making e-textiles: conductive yarn,conductive fabric,and conductive ink. Different options to protect the conductive materials are explored,such as water-resistant coating,thermoplastic urethane (TPU) film lamination,and dielectric ink printing. Electrical resistance as a function of laundry cycles is used to characterize the performance of the conductive materials. After the intended laundry cycles,samples were inspected under optical microscope and SEM to provide further insight on the performance of these materials.

Cleanliness is a product of design,including component density,standoff height and the cleaning equipment’s ability to deliver the cleaning agent to the source of residue. The presence of manufacturing process soil,such as flux residue,incompletely activated flux,incompletely cured solder masks,debris from handling and processing fixtures,and incomplete removal of cleaning fluids can hinder the functional lifetime of the product. Contaminates trapped under a component are more problematic to failure. Advanced test methods are needed to obtain “objective evidence” for removing flux residues under leadless components. Cleaning process performance is a function of cleaning capacity and defined cleanliness. Cleaning performance can be influenced by the PCB design,cleaning material,cleaning machine,reflow conditions and a wide range of process parameters. This research project is designed to study visual flux residues trapped under the bottom termination of leadless components. This paper will research a non-destructive visual method that can be used to study the cleanability of solder pastes,cleaning material effectiveness for the soil,cleaning machine effectiveness and process parameters needed to render a clean part. The test vehicle for this research study will be an engineered glass ceramic test substrate. The test substrate is transparent,precise and can be used for repeated studies. The ceramic engineered components are mounted to the substrate in a series of columns and rows. The standoff gap is 60µm and gap between components is 300um. Flux vehicles from many industry specific no-clean solder pastes will be included in this study. The response variable of the percentage of flux cleaned under the ceramic dies will be collected using an AOI machine and from optical imaging. This study will report the potential for cleaning flux residues trapped under leadless components when processed in aqueous spray batch cleaning tools using a next generation cleaning agent.

Cleanliness is a product of design,including component density,standoff height and the cleaning equipment’s ability to deliver the cleaning agent to the source of residue. The presence of manufacturing process soil,such as flux residue,incompletely activated flux,incompletely cured solder masks,debris from handling and processing fixtures,and incomplete removal of cleaning fluids can hinder the functional lifetime of the product. Contaminates trapped under a component are more problematic to failure. Advanced test methods are needed to obtain “objective evidence” for removing flux residues under leadless components. Cleaning process performance is a function of cleaning capacity and defined cleanliness. Cleaning performance can be influenced by the PCB design,cleaning material,cleaning machine,reflow conditions and a wide range of process parameters. This research project is designed to study visual flux residues trapped under the bottom termination of leadless components. This paper will research a non-destructive visual method that can be used to study the cleanability of solder pastes,cleaning material effectiveness for the soil,cleaning machine effectiveness and process parameters needed to render a clean part. The test vehicle for this research study will be an engineered glass ceramic test substrate. The test substrate is transparent,precise and can be used for repeated studies. The ceramic engineered components are mounted to the substrate in a series of columns and rows. The standoff gap is 60µm and gap between components is 300um. Flux vehicles from many industry specific no-clean solder pastes will be included in this study. The response variable of the percentage of flux cleaned under the ceramic dies will be collected using an AOI machine and from optical imaging. This study will report the potential for cleaning flux residues trapped under leadless components when processed in aqueous spray batch cleaning tools using a next generation cleaning agent.

The requirement to reconsider traditional soldering methods is becoming more relevant as the demand for bottom terminated components (QFN/BTC) increases. Thermal pads under said components are designed to enhance the thermal and electrical performance of the component and ultimately allow the component to run more efficiently. Additionally,low voiding is important in decreasing the current path of the circuit to maximize high speed and RF performances. The demand to develop smaller,more reliable,packages has seen voiding requirements decrease below 15 percent and in some instances,below 10 percent. Earlier work has demonstrated the use of micro-fluxed solder preforms as a mechanism to reduce voiding. The current work builds upon these results to focus on developing an engineered approach to void reduction in leadless components (QFN) through increasing understanding of how processing parameters and a use of custom designed micro-fluxed preforms interact. Leveraging the use of a micro-fluxed solder preform in conjunction with low voiding solder paste,stencil design,and application knowhow are critical factors in determining voiding in QFN packages. The study presented seeks to understand the vectors that can contribute to voiding such as PCB pad finish,reflow profile,reflow atmosphere,via configuration,and ultimately solder design. A collaboration between three companies consisting of solder materials supplier,a power semiconductor supplier,and an electronic assembly manufacturer worked together for an in-depth study into the effectiveness of solder preforms at reducing voiding under some of the most prevalent bottom terminated components packages. The effects of factors such as thermal pad size,finish on PCB,preform types,stencil design,reflow profile and atmosphere,have been evaluated using lead-free SAC305 low voiding solder paste and micro-fluxed preforms. Design and manufacturing rules developed from this work will be discussed.

Leadless semiconductor plastic packages (QFN) is a growing package category in terms of market share and diversity. This is also valid for low pin count semiconductors (e.g.: transistors and diodes). Several semiconductor companies offer a wide variety of leadless packages for such products. For small,low pin count products,these leadless packages are known as DFN (Discrete Flat No leads) packages. The diversity of DFN packages is still growing. There are several advantages of DFN packages compared to conventional leaded (SO) packages. A disadvantage is that the quality of the AOI inspection of the solder joint on the PCB is limited because the device terminals are only at the bottom of the products. The best way to inspect the soldering quality on PCB is x-ray inspection. However,especially automotive customers have requested suppliers to find a reliable alternative solution. In response to the requests to enable AOI (Automatic Optical Inspection) capability for leadless packages,side wettable flanks for DFN packages have been invented. With the help of side wettable flanks,a satisfactory wetting with solder during reflow soldering process at SMT can be guaranteed. The resulting solder fillet can be reliably inspected with AOI systems. An additional benefit is that the mechanical robustness on PCB could be improved (e.g.: higher device shear force). This paper describes the evolution from leaded to leadless semiconductor (DFN) low pin count packages. It will include a survey of standard semiconductor low pin count leaded and DFN packages. The realization and boundaries of side wettable flanks will be discussed. Focus is on side wettable flanks for 3 to 6 I/Os DFN packages. Alternatives for >6 I/Os packages are considered: e.g.: “dimple”,saw plate saw and immersion Sn plating. Verification of AOI capability as done together with a leading AOI system supplier complete this paper.

The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV),trenches,through holes (TH),and pillar bumps. As circuit miniaturization continues,developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios,while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time,presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative,one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented. The direct current (DC) process is studied in a wide variety of conditions to collect information on its capabilities. The plating conditions allowing improved micro-distribution for the plated TH are discussed. Boards with various thicknesses and TH aspect ratios are included in this study. The responses included TP min.,TP knee,via dimple and cavity formation. A strong interaction between brightener and leveler concentrations was found. The results obtained allow for enhancing through hole micro-distribution while filling a wide range of BMV sizes. The process is designed for a variety of equipment applications with insoluble anodes,including vertical continuous plating equipment. In addition,a modified formula for soluble anodes applications is described. Filling of through via holes in core layers of HDI and IC substrates in a one-step DC process is also demonstrated. Through vias filled with <5 microns or zero dimple and no voids or defects are shown. Mechanical properties,tensile strength => 42,000 psi,elongation > 20% as well as the thermal resistance of copper deposits met and exceeded the IPC standards thus satisfying the need of a highly reliable copper electroplating process.