Driven by miniaturization,cost reduction and tighter requirements for electrical and thermal performance,the use of lead-frame based bottom-termination components (LF-BTC) as small-outline no-leads (SON),quad-flat no leads (QFN) packages etc.,is increasing. However,a major distractor for the use of such packages in high-reliability applications has been the lack of a visible solder (toe) fillet on the edge surface of the pins: because the post-package assembly singulation process typically leaves bare copper lead frame at the singulation edge,which is not protected against oxidation and thus does not easily solder-wet,a solder fillet (toe fillet) does not generally develop. Solder-joint robustness is also increased by the presence of a robustly wettable singulation edge,but this is not the primary benefit (the number of cycles to failure under thermal cycling is typically decreased by up to about 25% in the absence of an outer,visible fillet). Users,primarily those involved in the mass production of high-reliability mission-critical (e.g. automotive) applications,have insisted that a solder fillet be visible at the outer edge of each contact to enable a robust inspection for wetting failures by automatic optical inspection (AOI). The possibility to inspect the integrity of the solder joints by AOI avoids the need to employ X-ray inspection methods,which involve additional costs and layout restrictions,as certain keep-out zones for traces and components are necessary for avoiding disturbing effects in the solder joints X-ray images. Package suppliers have responded to these needs with various pin modifications that enable a portion of the terminal-edge surface to remain plated after singulation,as two-step sawing or dedicated etching processes. However,for such pin modifications to be useful in the context of AOI under series production conditions,the pin modifications must meet certain geometrical requirements,in order to robustly distinguish a wetted pin (‘good solder joint) from a non-wetted pin (‘defective solder joint’) in AOI. These geometrical requirements will be investigated in this work considering also typical assembly-related process variations. The geometrical requirements enabling robust AOI of LF-BTCs in mass production will be derived.

The miniaturization trend is driving industry to adopting low standoff components. The cost reduction pressure is pushing telecommunication industry to combine assembly of components and electromagnetic shield in one single reflow process. As a result,the flux outgassing is getting very difficult for devices. This resulted in more large voids. For a properly formulated flux,there is less outgassing at temperature above melting temperature of solder or the flux can be expelled out from interior of solder joints due to good wetting ability. Either approach will reduce the voids. In this work,a new halogen-free no-clean flux chemistry,F,has been developed. The solder paste using 96.5Sn3.0Ag0.5Cu and Alloy A exhibited ultra-low voiding and virtually zero solder beading performance. The low voiding performance on Alloy A solder paste is particularly crucial since the automotive industry has been ailing by the poor voiding performance of this 6-element solder alloy system. The halogen-free F virtually enables the automotive to migrate toward full adoption of high reliability 6-element alloy system. Furthermore,the hot slump,wetting,solder balling,and graping performance are all acceptable. The printing performance of F showed excellent transfer efficiency under various printer setup and pad design conditions,indicating this flux system is a very robust system for SMT fine-pitch applications.

Creep corrosion on printed circuit boards (PCBs) is the corrosion of copper metallization and the spreading of the copper corrosion products across the PCB surfaces to the extent that they may electrically short circuit neighboring features on the PCB. The iNEMI technical subcommittee on creep corrosion has developed a flowers-of-sulfur (FOS) based test that is sufficiently well developed for consideration as an industry standard qualification test for creep corrosion. This paper will address the important question of how relative humidity affects creep corrosion. A creep corrosion tendency that is inversely proportional to relative humidity may allow data center administrators to eliminate creep corrosion simply by controlling the relative humidity in the data center,thus,avoiding the high cost of gas-phase filtration of gaseous contamination. The creep corrosion relative humidity dependence will be studied using a modified version of the iNEMI FOS test chamber. The design modification allows the achievement of relative humidity as low as 15% in the presence of the chlorine-releasing bleach aqueous solution. The paper will report on the dependence of creep corrosion on humidity in the 15 to 80% relative humidity range by testing ENIG (gold on electroless nickel),ImAg (immersion silver) and OSP (organic surface preservative) finished PCBs,soldered with organic acid flux.

Reliability Expectations of Highly Dense Electronic Assemblies is commonly validated using Ion Chromatography and Surface Insulation Resistance. Surface Insulation Resistance tests resistance drops on both cleaned and non-cleaned circuit assemblies. It is well documented in the literature that SIR detects ionic residue and the potential of this residue to cause leakage currents in the presence of humidity and bias. Residues under leadless components are hard to inspect for and to ensure flux residue is totally removed. The question many assemblers consider is the risk of residues that may still be present under the body of components. A recent research study10 of both flux activator systems and cleaning under bottom terminated components found that different no-clean flux packages have chemical properties that induce failure at different rates. The study also found that residues that were not fully cleaned under leadless components could be a reliability risk. Electrochemical methods (EIS) provide insight into the corrosion potential of a residue,in this case,flux residue. Electrochemical methods have not been commonly used for assessing corrosion potential on electronic devices. The purpose of this research study is to run Electrochemical Methods on the four flux systems used in the SIR study to determine if EIS data findings have commonality on the SIR data findings.

Creep corrosion testing of printed circuit boards (PCBs) using a specially designed flowers of sulfur chamber has been developed by an iNEMI technical committee. The iNEMI test is based on a chamber that is 300-mm cube acrylic box with 8-paddle wheels rotating at 20 RPM that can accommodate 8 PCBs. In one embodiment of the test setup,the sulfur vapor with controlled concentration is provided by two 100-mm diameter petri dishes containing beds of sulfur and by maintaining the chamber temperature at 50oC. The relative humidity is maintained at 81% using two 80-mm diameter petri dishes containing KCl saturated solution. The source of chlorine,while repeatable though time varying in concentration,is provided by 40-ml household bleach in a 100-ml beaker. The creep corrosion qualification test has successfully predicted creep corrosion on specially designed and manufactured unpopulated printed circuit boards of various finishes,soldered with rosin or with organic acid flux. Creep corrosion similar in morphology to that observed in the field has been reproduced in the iNEMI tests. This paper describes the iNEMI creep corrosion testing of a number of fully populated PCBs of various technologies and vintages of known field reliability. The results confirm the finding that prebaking the PCBs is a necessary condition for creep corrosion to occur in the iNEMI flowers of sulfur chamber. The creep corrosion results on prebaked PCBs of 7 different technologies agreed with the field reliability experiences. The PCBs from lots that suffered creep corrosion in the highly polluted geographies showed creep corrosion of similar morphology in the flowers of sulfur creep corrosion test; whereas,the PCBs from lots that did not suffer creep corrosion in the field,survived the flowers of sulfur test with little or no creep corrosion. The iNEMI PCB creep corrosion qualification test is now sufficiently well developed to be adopted as an industry standard test. The paper will also show some evidence that long-term storage before usage may eliminate creep corrosion.

Millimeter-wave (mmWave) frequency applications are becoming more common. There are applications utilizing PCB technology at 60 GHz,77 GHz and many other mmWave frequencies. When designing a PCB for mmWave frequency,the properties of the circuit materials need to be considered since they can be critical to the success of the application. Understanding the properties of circuit materials at these frequencies is very important. This paper will give an overview of which circuit material properties are important to mmWave frequency applications using PCBs. There will be data supplied which demonstrates why these properties are essential to the circuit material selection for mmWave applications. Some properties discussed will be dielectric constant (Dk) control,dissipation factor,moisture absorption,thickness control and TCDk (Temperature Coefficient of Dk). Measured comparisons will be shown for insertion loss and Dk versus frequency for different types of circuit materials up to 110 GHz. As part of the test data,the impact on circuit performance due to TCDk and moisture absorption will be shown at mmWave frequencies.

Higher functionality,higher performance and higher reliability with smaller real estate are the mantras of any electronic device and the future guarantees more of the same. In order to achieve the requirements of these devices,designs must incorporate fine line and via pitch while maintain good circuitry adhesion at a smooth plating-resin interface to improve signal integrity. The Semi-Additive Process (SAP) is a production-proven method used on low dielectric loss tangent (Df) build-up materials that enables the manufacture of ultra-fine circuitry. The standard SAP process utilizes some roughening or texturing of the dielectric substrate in order to achieve sufficient adhesion; however,the rough surface at the plating-resin interface potentially increases transmission loss at high signal speeds. To promote signal integrity at high-frequency signal transmission,the next SAP process should provide high plating-resin adhesion as well as very smooth interface in between. The next build-up material in demand should present high thermal and dimension stability,good chemical resistance to survive many cure and reflow processes in circuitry manufacture. It should also deliver excellent electric properties including high insulation reliability,low Df and low dielectric constant (Dk) to guarantee good signal integrity in high frequency signal transmission. Meanwhile,the good properties above bring challenges to the SAP process. This paper will discuss a new SAP process for low loss build-up materials with low desmear roughness (Ra= 40-100 nm) and excellent adhesion (610-680gf/cm) at various processing conditions. Along with the process flow,the current work will also present results and a discussion regarding characterization on the morphology and composition of resin and/or metal plating surfaces using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX),surface roughness analysis,plating-resin adhesion evaluation from 90o peel tests.

Six decades of legacy experience makes the specification and production of screens and masks to produce repeatable precision results mostly an exercise in matching engineering needs with known ink and substrate performance to specify screen and stencil characteristics. New types of functional and electronic devices,flex circuits and medical sensors,industrial printing,ever finer circuit pitch,downstream additive manufacturing processes coupled with new substrates and inks that are not optimized for the rheological,mechanical and chemical characteristics for the screen printing process are becoming a customer driven norm. Many of these materials do not work within legacy screen making,curing or press set-up parameters. Many new materials and end uses require new screen specifications. This case study presents a DOE based method to pre-test new materials to categorize ink and substrate rheology,compatibility and printed feature requirement to allow more accurate screen recipes and on-press setting expectations before the project enters the production environment where time and materials are most costly and on-press adjustment methods may be constrained by locked,documented or regulatory processes,equipment limitations and employee experience.

One of the major concerns with screen printing of low temperature curing polymer thick film (PTF) pastes onto common flexible PET substrate materials is the overwhelming spread of the paste beyond the design line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This issue prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other,more involved and more costly patterning methods. In many cases,flexible circuit fabricators desiring finer more accurate circuit elements may have to subcontract parts out of house in order to incorporate other patterning methods and in-turn lose control of both cost and lead time to the hands of their subcontracting partners. This paper will provide results of numerous in-house and field testing,comparing printed line width control,edge definition,and improved conductivity of printed polymer Ag conductors on different flexible PET substrates with testing done on a company developed screen emulsion stencil material and substrate material.

This study investigates the scooping effect during solder paste printing as a function of aperture width,aperture length and squeegee pressure. The percent of the theoretical volume deposited depends on the PWB topography. A typical bimodal percent volume distribution is attributed to poor release apertures and large apertures,where scooping takes place,yielding percent volumes <100%,while SMD apertures and apertures near PWB features that raise the stencil yield percent volumes >100%. This printing experiment is done with a concomitant validation of the printing process using standard 3D Solder Paste Inspection (SPI) equipment. The data collected from the SPI equipment included the solder paste volume,printed area,solder paste height and x-y offset printing. The volume data for each aperture width exhibits a Gaussian distribution,with the mean and standard deviation changing as a function of aperture width. For small apertures poor release is observed,while the reduction of the solder paste volume for large apertures is attributed to the appearance of the scooping effect at 0.070” aperture width. The Gaussian distributions,when analyzed separately,indicate that the printing process for each aperture width is under control yielding C-pk greater than 1.33 (DPMO <63),with USL and LSL set at ±20% from the mean volume. We also investigated the release of apertures with and without round corners. The former exhibited better solder paste release.