High pressure capillary IC allows you to:
Lower operational costs – water,waste,consumables
“Always Ready”
Improved system and analytical performance
Convenience
Rush samples
Enables high-resolution separations and Fast IC separations using new 4 µm particle columns
Expand separation capabilities
Smaller particle columns
Faster flow rates
Higher eluent concentrations using RFIC chemistry

With the ever-present pressure toward miniaturization in electronic devices,smaller distances between traces and component terminations are likely to increase the devices’ sensitivity to contamination scenarios that may cause current leakage. Traditionally,with “no-clean” processes,the focus has been on the conductivity of flux residues,which can be measured with industry accepted techniques such as IPC J-STD-004B SIR (Surface Insulation Resistance) testing (IPC-TM-650 2.6.3.7). However,the manufacturing environment,especially in low-cost labor markets,and even on otherwise well-controlled shop floors,may be far from representative of the “perfect world.” Other materials may find their way on to the surface of the PCB,often introduced through negligent human activity and handling that may or may not have a negative impact on the electrical reliability of the device. This paper will discuss an experiment that was performed to investigate the effects of “contaminants” that could be measured with SIR testing. The contaminants were tested by themselves as well as in conjunction with a halogen-free,Pb-free,no-clean solder paste. The materials investigated as contaminants were: human skin oil/perspiration,high temperature reflow oven chain oil,pepperoni pizza grease,hand cream/lotion,and tap water.

•Developments of Printed FPCs
- PE resist for long FPCs
- Flexible Touch Sensor Panel(TSP) application
- Single-sided Printed FPCs
- Double-sided Printed FPCs
- Smart Printed FPCs

•Photonic curing uses high-intensity flash lamps to selectively heat target materials.
•The PulseForge tools are based on the patented use of photonic curing and are designed for use in development and production.
•Photonic curing is used for drying,sintering,reacting,and annealing. The use of the tools enables exciting new types of materials to be used in printed electronics,such as the copper oxide reduction inks.
•The Metalon ICI series of copper oxide reduction inks are formulated with a reducing agent to convert copper oxide to copper thin film on the substrate after printing. Sheet resistance < 20 mOhm/sq.
•Applications impacted include RFID,displays,photovoltaics,sensors,and others.
•Many opportunities for innovation and competitive advantage are still open.
•We have introduced an R&D photonic curing system,the PulseForge 1200,to accelerate this development.

Nanotechnology is a key enabling technology for printed electronics. Low temperature reactivity,reaction speeds,flexibility and fine pitch considerations dictate that nanomaterials should be given serious consideration in many of the process steps in printed electronics.

This study was conducted to understand seven materials reliability,behavior of Dielectric constant and Dissipation factor over medium to high frequencies. A modified version of HDPUG design was used for evaluation. This test board contains IST,CAF,Thermal Cycling and Impedance (both Micro Strip and Strip line) coupons. In addition to these we added HATS coupons. Materials were chosen from FR4 family and selection was made based upon our present and future needs. Dielectric constants of these materials ranged from Dk 3.6 to Dk 4.2,as published,at 10GHz. This document shows the effect of Dk and Df values from 10GHz to 20GHz and also shows their performance for lead free assembly process when tested using IST and HATS test methods. In addition CAF testing was done on five of the seven materials.

The need in complexity for microwave space products such as active BFNs (Beam Forming Networks) is increasing,with a significantly growing number of amplitude / phase control points (number of beams * numbers of radiating elements). As a consequence,the RF component’s package topology is evolving (larger number of I/Os,interconnections densification ...) which directly affect the routing and architecture of the multilayer boards they are mounted on. It then becomes necessary to improve the density of these boards. It has already been demonstrated the benefits of non-PTFE (Teflon®) materials for the manufacturing of microwave multilayer PCBs. The Liquid Crystal Polymer (LCP) is a very interesting candidate allowing,among others,to achieve RF and LF flexible interconnections. It has many advantages for packaging applications or manufacturing multilayer structures (low dielectric constant and losses,low water absorption,low CTE in X and Y axis…). Mostly,this material is available in very thin layers,allowing to considerably reduce the total thickness of the board and favoring densification (decrease of via diameter,pads,track width...). However,the use of LCP for printed circuit board is fairly recent and few manufacturers have experience with this material. This paper will present the work performed to achieve LCP-based high density multilayer structures,describing the different electrical and technological breadboards manufactured and tested and presenting the results obtained.

During the production of Lead-Free Hot Air Solder Leveling (LF HASL),non-wetting issues in several components were found including BGA pad. The common visual aspect of the suspicious pads was the typical yellowish and bluish color. However,during traditional Scanning Electron Microscopy/Electron Dispersive X-Ray Spectroscopy (SEM/EDX) analysis for wetting issues only a small increasing of copper was found but not related to the problem. Because of that,Time-Of-Flight Secondary Ion Mass Spectroscopy (TOF SIMS) analysis was proposed; using this technique,we could achieve better surface analysis in which we found the root cause on non-wetting just in nanometers of penetration.
With this non-common tool,the results showed something not detected before: the yellowish were zones with different thick oxide layers (about 250 nm) undetectable by SEM/EDX -four times higher than a normal oxide thickness. Consequently,solder paste flux was not able to clean that oxide thickness and joints were not formed properly. The oxide is expected to be Sn2O3 and not SnO2,the most common tin oxide. In this part,we would also conclude the activation level of solder paste flux depends on the type of oxide. With this information,an investigation was conducted to remove the oxide layer as much as possible,so a solder paste with a flux more suitable to eliminate it was implemented and a cleaning process was designed to reduce it. These actions decreased the defects. In conclusion,TOF-SIMS analysis is a tool to understand better the solderability topics in Electronics Industry.

Interposer technologies are gathering more importance in IC packaging as the industry continues miniaturization trends in microfabrication nodes and IC packaging to meet design and utility needs in consumer electronics. Furthermore,IC packaging is widely seen as a method to prolong Moore’s law. Historically,silicon has been the material of interest for interposer materials given its prevalence in IC production,but it presents many technical and costs hurdles. In contrast,glass interposer technology presents a low cost alternative,yet attempts at producing advanced through glass vias (TGVs) arrays using traditional methods,such as laser ablation,have inherent process flaws,such as reduced interposer mechanical strength and debris sputtering among others.
In this extended abstract we present 3D Glass Solutions’ efforts in using our proprietary APEX™ Glass ceramic to create various interposer technologies. This extended abstract will present on the production of large arrays of 10 micron diameter TGVs,with 20 micron center-to-center pitch,in 100 micron thick APEX™ Glass ceramic and the comparisons of wet etching of APEX™ Glass vs. laser ablation.

The Printed Circuit Board (PCB) is the backbone of electronics and a large number of consumer devices. The challenge to put more function in a smaller space requires more components utilizing smaller bond pads,smaller lines and tighter pitch. The electronic packaging industry has aggressively pursued novel ways to shrink and stack multilayer boards inside smaller volumes. Industry is approaching serious obstacles in the continued size reduction requirements with the need for wires,epoxy,vias,solder and sometimes bolts and screws to mount the boards. The next logical step is to move beyond 2D stacking,which is 2.5D to make 3D packages and to utilize the 3rddimension directly. Eliminate the traditional 2D FR4 board and the wires,epoxies,vias and solder and make the next generation packages utilizing the 3rddimension; the Printed Circuit Structure (PCS). The PCS concept will allow passives,actives and even antennas to move out of the XY plane and into the XZ and YZ planes. This new dimension will appear to be very complex and next generation circuit optimization will be required,but the end result will net a significant improvement in volume utilization. In addition,if new materials are developed and utilized properly,the PCS will be the box or the package thus eliminating all the bolts and screws necessary to mount a PCB in a traditional box or package,thus again saving space and reducing weight. nScrypt and the University of Texas at El Paso will present 3D Printing of Printed Circuit Structures. A demonstration of true 3D electronic structures will be demonstrated and shown as well novel approaches which utilize Computer Aided Design (CAD) to 3D Printing which will include the electronics portion.