The Pin in Paste (PiP) technology is the process of soldering Pin through hole (PTH) components using the Surface Mount Technology (SMT) reflow process. The use of PiP process offers several advantages compared to the traditional wave soldering process. One of the primary advantages is lowering of cost due to the elimination of the wave soldering process and its associated tooling cost and potential handling damage. Another advantage is that with the wave soldering process,it is extremely difficult to achieve adequate holefill on thermally challenging thick Printed Circuit Boards (PCBs). However,by using PiP process with combination of solder preforms,it is possible to achieve adequate holefill and reliable solder joints for soldering PTH components.
The objective of this study is to investigate the use and limitations of machine-placed solid solder preforms during the top-side SMT reflow process for PTH components. An experiment was designed to investigate the following problems:
1) How much additional volume is provided by the combination of printed solder paste plus preforms in determining final barrel fill volume?
2) How far away from the hole can the paste and preform extend and still coalesce during reflow?
3) What is the optimum lead to hole ratio for the use of solder preforms?
4) What is the effect of pin protrusion on the PiP process?
5) What are the limitations in placing preforms within printed solder paste?
6) What are the design considerations required for the different / various PTH components to be suitable for the PiP process with solder preforms?
7) What is the effect of different types of solder masks on the PiP process?
The experiment was conducted on a 130 mil test vehicle using both tin-lead and lead-free materials and processes. The results of this designed experiment along with the inspection methods are presented and discussed in detail in this paper. The outcome of this study will thus provide process engineers extensive guidelines for implementing PiP technology with combination of solder preforms.

Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size,such as a near die size footprint,thin profile,and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size,weight,electrical,and thermal properties are important. However,adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow,outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength,ductility,creep,and fatigue life. In addition,voids could also produce spot overheating,lessening the reliability of the joints. This is particularly a concern for QFN where the primary function of thermal pads is for heat dissipation. Thermal pad voiding control at QFN assembly is a major challenge due to the large coverage area,large number of thermal via,and low standoff. Both design and process were studied for minimizing and controlling the voiding. Eliminating the thermal via by plugging is most effective in reducing the voiding. For unplugged via situations,a full thermal pad is desired for a low number of via. For a large number of via,a divided thermal pad is preferred due to better venting capability. Placement of a thermal via at the perimeter prevents voiding caused by the via. A wider venting channel has a negligible effect on voiding and reduces joint continuity. For a divided thermal pad,the SMD system is more favorable than the NSMD system,with the latter suffering more voiding due to a thinner solder joint and possibly board outgassing. Performance of a divided thermal pad is dictated by venting accessability,not by the shape. Voiding reduction increases with increasing venting accessability,although the introduction of a channel area compromises the continuity of the solder joint. Reduced solder paste volume causes more voiding. Short profiles and long hot profiles are most promising in reducing the voiding. Voiding behavior of a QFN is similar to typical SMT voiding and increases with pad oxidation and further reflow.

Although many have predicted the demise of through-hole components,they are alive and well with tens of billions assembled each year. In many cases these components are assembled by wave soldering. However,in many mixed product technology (i.e. SMT and through-hole on the same board) products,it makes sense to consider assembling the through-hole components with the pin-in-paste (PIP) process. PIP has been successfully used for several decades now; however in many cases it is not possible to print enough solder paste to obtain an acceptable solder joint. In addition to this “solder starved” condition,the large quantity of solder paste used to form the though-hole joint,results in excess residual flux. This residual flux can lead to difficulties in in-circuit testing and potential surface insulation resistance concerns.
In light of the above need,solder performs have been developed. These slugs of solder typically come in the same sizes as 0402,0603,and 0805 passive components. The solder preforms are placed by the component placement machines onto the solder deposit. This additional solder assures that an adequate solder joint is formed with a minimum of solder paste and its residual flux.
Although PIP was an early application of solder preforms,more recently other “solder starved” applications have emerged such as radio frequency (RF) shields and connectors. In addition,the use of ultra thin stencils in the assembly of miniaturized components can result in some other components being solder starved and hence,are candidates for solder performs.
This paper will cover the design and assembly techniques for using of solder performs in the “solder fortification” needs described above. Several successful applications will be presented. In some of these applications,defects were reduced by 95% after implementing solder performs.

Silicones have been used in the electronics industry as protective/assembly materials for operations that will have a wide temperature variation. A large variety of silicone products are available to satisfy the needs for the majority of these operations,including: coatings,adhesives and encapsulants. Special kinds of encapsulants,subject matter of this study,are the gels. Silicone gels are a special kind of encapsulating materials with unique characteristics. They are extremely soft elastomers (solids with liquid characteristics) that are used to provide high levels of stress relief to sensitive circuitry when operating at adverse environments. They provide protection by functioning as dielectric insulators,forming environmental barriers and relieving mechanical and thermal stress on components.
Advances in miniaturization technologies have had dramatic impacts on our lives. Radios,computers,and telephones that once occupied large volumes now fit in the palm of a hand. This miniaturization has brought the need to use more delicate components/circuits that have to work in harsh environments and withstand exposures to high or low temperatures. Silicone gels are products that gather many of the special requirements to protect these sensitive assemblies working in a highly demanding environment. The purpose of this paper is to explore the performance of silicones gels when operating at high or low temperature to better establish the reliability temperature limits for these kinds of products.

The most common epoxy encapsulation compounds available on the market utilise specialised fillers,such as Alumina trihydrate (ATH),to provide a high level of flame retardancy. Such fillers decompose endothermically at 200°C producing water which cools the substrate. This inhibits the effects of the ignition source and reduces the substrates’ ability to sustain a flame. Such fillers are therefore extremely efficient and as such are utilised in many applications where high operating temperatures and viscosity are not crucial requirements for the user. Due to the decomposition temperature being relatively low,the stability of encapsulation compounds which incorporate ATH in their formulation are limited above 150-200°C. In addition,the use of such fillers dramatically increases the viscosity,making the resins difficult to work with when encapsulating complicated geometries or where space is limited. To overcome these limitations,a novel flame retardant system has been investigated. Although still a filler,approximately 10 times less material is required to produce a flame retardant system,therefore making it possible to formulate a flame retardant encapsulation resin with viscosities of less than 700mPa s,whilst still meeting UL94 V-0. In addition,this novel system does not decompose at temperatures around 200°C and exhibits excellent stability at very high temperatures,including those seen in typical reflow profiles. This paper details the advantages of this novel flame retardant system,highlighting the performance advantage over standard metal hydroxide fillers and concludes with possible applications when formulated into an encapsulation resin.

Coating adhesion has been a difficult property to measure,and the industry has made do with a scratch test that is only capable of qualitative tests. NPL with industrial partners,have developed a tape peel test that can be applied to the PCB or component surface. The choice of tape is critical in achieving complete wetting of the fabric,and good adhesion to the coating. The tape is applied with liquid coating to the substrate,and then cured,leaving a flying unbonded section for clamping on during the pull test. The method shows clear differences in adhesion between different coating types: acrylics,polyurethanes and silicones. The effect on coating adhesion of surface cleanliness and the cure state of the resist were investigated. Coatings were generally observed to perform well with these problems. However,coating adhesion to components and some resists proved much more variable,with some coatings failing to adhere to problematic components. Surface energy measurements using a wetting angle technique were also used and compared with the peel data.

High levels of residual moisture in PCBs are problematic and can result in delamination during soldering and rework. Moisture accumulates during storage and industry practice recommends specific levels of baking to avoid delamination. This paper will discuss the use of capacitance measurements to follow the absorption and desorption behaviour of moisture. The PCB design used in this work,focused on the issue of baking out moisture trapped between copper planes. The PCB was designed with different densities of plated through holes and drilled holes in external copper planes,with capacitance sensors located on the inner layers. For trapped volumes between copper planes,the distance between holes proved to be critical in affecting the desorption rate. For fully saturated PCBs,the desorption time at elevated temperatures was observed to be in the order of hundreds of hours. Finite difference diffusion modelling was carried out for moisture desorption behaviour for plated through holes and drilled holes in copper planes. A meshed copper plane was also modelled evaluating its effectiveness for assisting moisture removal and decreasing bake times. Results also showed,that in certain circumstances,regions of the PCB under copper planes initially increase in moisture during baking.

As part of High Density Packaging Users Group (HDPUG) Pb-Free Board Materials Reliability Project 2,the moisture sensitivity of various lead-free laminates and the effect of moisture uptake on the material survivability through Pb-free reflow were studied using capacitance measurements and time-domain reflectometry (TDR) impedance measurements. WIC-20 coupons were used as test vehicles. In this paper,results from 20 different laminate materials will be summarized. The relationship between moisture uptake and material survivability through Pb-free reflow will be discussed.

Moisture can accelerate various failure mechanisms in printed circuit board assemblies. Moisture can be initially present in the epoxy glass prepreg,absorbed during the wet processes in printed circuit board manufacturing,or diffuse into the printed circuit board during storage. Moisture can reside in the resin,resin/glass interfaces,and micro-cracks or voids due to defects. Higher reflow temperatures associated with lead-free processing increase the vapor pressure,which can lead to higher amounts of moisture uptake compared to eutectic tin-lead reflow processes. In addition to cohesive or adhesive failures within the printed circuit board that lead to cracking and delamination,moisture can also lead to the creation of low impedance paths due to metal migration,interfacial degradation resulting in conductive filament formation,and changes in dimensional stability. Studies have shown that moisture can also reduce the glass-transition temperature and increase the dielectric constant,leading to a reduction in circuit switching speeds and an increase in propagation delay times. This paper provides an overview of printed circuit board fabrication,followed by a brief discussion of moisture diffusion processes,governing models,and dependent variables. We then present guidelines for printed circuit board handling and storage during various stages of production and fabrication so as to mitigate moisture-induced failures.

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