Sculpted Flex Circuits are a very cost effective,low profile termination solution that is not very well known. These Flex Circuit hybrids can provide the user a simple interconnection between circuit boards or a circuit boards and anything else,which does not require connectors. This eliminates the need for the space taken up on a circuit board by traditional connectors. Sculpted Flex Circuits can carry high current/voltage and can be shielded for signal integrity. And they can easily be fabricated from commercially available materials,with standard PWB processes and be certified to common DOD and industry specifications. This presentation will define the Sculpted Flex Circuit,explain the fabrication techniques and explore common applications. The most interested audience will be the designers,technicians,engineers and systems people at the EMS to OEM level.

Backward Compatibility of Pb free SnAgCu (SAC) solders with conventional SnPb soldering has been a subject of considerable interest since the introduction of Pb free solders earlier in this decade. Most BGA package suppliers have converted their BGAs ball alloys to Pb free,using SAC solder. Some customers for these BGA packages,whose products have exemptions from the use of Pb free solders,are still employing SnPb solder paste for reflow soldering their products. The two main concerns with Backward Compatibility are the quality and reliability of the solder joints formed when mixing SAC solder balls of the BGA with eutectic SnPb solder paste. Acceptable mixing of the two alloys is critical for solder joint yields during high volume manufacturing,as well as for long-term solder joint reliability in the field.
One key challenge to maximizing both the solder joint yield and reliability has been to achieve adequate collapse of the SAC solder balls and sufficient Pb mixing when the reflow soldering process is performed at temperatures below the Pb free solder liquidus temperature. Backward Compatible reflow profile development has always been a challenge,but recently,this challenge has been further exacerbated by the increase in size and complexity of high density BGAs.
This paper will illustrate the challenges encountered in reflow profiling of a thick (>90mils),printed circuit board test vehicle,which contains four each of two large (>37mm,>1200 balls),high density BGAs. The ball collapse and the percentage of Pb mixing achieved in the solder joints of these BGAs during the various iterations of the reflow profile development will be presented. The impact of package dynamic warpage during the reflow soldering process,on the solder joint shape,collapse and percentage of Pb mixed within a solder joint will also be described As part of the study,recommendations will be made for an optimum reflow window that can be used to achieve acceptable degree of mixing in
solder joint formation.

Pad cratering in Printed Circuit Boards (PCBs) is typically associated with lead-free products. This paper addresses laminate materials and the failures associated with the higher Pb-Free reflow temperatures and the acceptability requirements for use in Pb-Free products. The use of testing methodology,including pad pull testing and IPC peel testing to rank materials and processes is investigated,with a general relationship between pad size and strength being offered. Two cases studies illustrate the value in pad pull testing.

Recently,the industry has seen the development of a wide range of new Pb-free alloys. A significant element of uncertainty within the industry regarding these new alloys is the lack of defined data requirements for alloy acceptance.
This paper describes the progress of recent efforts to standardize Pb-free solder alloy testing requirements. Hewlett-Packard,the iNEMI consortium,the Solder Products Value Council,and the IPC are working together to create such standards. To facilitate the standardization of alloy testing,the required tests are divided into three major areas,each of which may be covered by a separate standard.
• Material properties
• Solder joint reliability
• Impact to manufacturing processes
This paper presents the status of standardization efforts in each of these three areas.

Package on Packages (PoP) find use in applications that require high performance with increased memory density. One of the
greatest benefits of PoP technology is the elimination of the expensive and challenging task of routing high-speed memory
lines from under the processor chip out to memory chip in separate packages. Instead,the memory sits on top of the
processor and the connections are automatically made during assembly. For this reason PoP technology has gained wide
acceptance in cell phones and other mobile applications. PoP technology can be assembled using one-pass and two-pass
assembly processes. In the one-pass technique the processor is first mounted to the board,the memory is mounted to the processor and the finished board is then run through the reflow oven in a single pass. The two-pass technique has an intermediate step in which the memory is first mounted onto the processor. Then,these two parts are placed in a carrier tray and reflowed. These joined devices are then mounted on the circuit board and the finished board is reflowed a second time. The two-pass technique has a distinct advantage in that the PoPs can be checked for defects before final assembly using a non-destructive test (such as X-Ray) and hence one would expect higher yield. For this study,identical test vehicles were assembled with eight PoP packages assembled with SAC105 and SAC125 solder for the bottom BGA and top BGA respectively. One-pass technique and two-pass technique were used to assemble two test vehicles each. These test vehicles were evaluated under mechanical torsion loading to establish if method of assembly used has any impact on the mechanical fatigue durability. This was followed by failure analysis to determine failure sites. Time to failure data was plotted as Weibull 2-parameter distributions and ANOVA analysis was performed. No statistically significant difference was found in the reliability of the packages assembled using the two different techniques.

Package on Package (PoP) has become a relatively common component being used in mobile electronics as it allows for saving space in the board layout due to the 3D package layout. To insure device reliability through drop tests and thermal cycling as well as for protecting proprietary programming of the device either one or both interconnect layers are typically underfilled. When underfill is applied to a PoP,or any component for that matter,there is a requirement that the board layout is such that there is room for an underfill reservoir so that the underfill material does not come in contact with surrounding components. The preferred method to dispensing the underfill material is through a jetting process that minimizes the wet out area of the fluid reservoir compared to traditional needle dispensing. To further minimize the wet out area multiple passes are used so that the material required to underfill the component is not dispensed at once requiring a greater wet out area. Dispensing the underfill material in multiple passes is an effective way to reduce the wet out area and decrease the distance that surrounding components can be placed,however,this comes with a process compromise of additional processing time in the underfill dispenser. The purpose of this paper is to provide insight to the inverse relationship that exists between the wet out area of the underfill reservoir and the production time for the underfill process.

The motivation for developing higher density IC packaging continues to be the market and the consumers’ expectation that
each new generation of products furnish greater functionality. The miniature IC package evolution began with the development of chip-scale and die-size package technology. These miniature IC package innovations proved ideal for portable and hand-held electronic applications. To address the need for even more functionality without increasing their products size,a number of companies have adapted various forms of multiple-die 3D packaging. A majority of these early multiple function devices relied on the sequential stacking of die elements onto a single substrate interposer. Because the wire-bonding of multiple tiers of uncased die is rather specialized and the die used may have had relatively poor wafer level yields or were not always available in a pre-tested (KGD) condition,overall manufacturing yield of the stacked-die packaged devices have not always met acceptable levels. A key advantage of the package-on-package process is that each layer of the package can be pre-tested before joining. This capability greatly improves the overall manufacturing yield and the functional reliability of the final package assembly is assured. The information furnished in this paper will focus PoP package
standards,substrate design criteria and assembly methodology for efficient in-line assembly processing of vertically stacked
IC package elements.

The reliability of an embedded planar capacitor laminate under a variety of environmental stress and bias conditions was investigated. The dielectric consisted of a composite of BaTiO3 particles in a bisphenol-epoxy matrix. The capacitor laminate was embedded in a 4-layer test board in which the power plane was etched to form discrete embedded capacitors having a common ground plane. Capacitors of two different areas were studied,having capacitances of about 400 pF and 5 nF.
The test vehicle with embedded capacitors was subjected to temperature and voltage aging and temperature-humidity-bias
(THB) tests at different stress levels. Three parameters,capacitance (C),dissipation factor (DF),and insulation resistance (IR),were measured in-situ during stress testing. Results are presented of testing at multiple stress levels in temperature and voltage aging tests and THB testing. Changes in electrical parameters during stress testing are reported,as well as the effects of stress conditions and levels on characteristic life. Physical analysis is used to identify the material response of the embedded capacitor laminate to the imposed stresses,providing the basis for recommendations regarding laminate design and usage.

Pad cratering in the PCB is a new failure mode encountered in electronic assemblies,particularly in lead-free products. The
failure mechanisms and root causes are not yet fully understood,and lack appropriate industry standard tests for PCB qualification with regard to pad cratering. This paper reviews major publications and research reports on various PCB materials from industry studies in this field. Various PCB tests,such as flexural strength test and pad strength test,have been studied. It is recommended that the qualification of the PCB can be done in two stages: PCB board level and PCBA product level. From those results,a new qualification method is suggested for screening out PCB pad cratering failures.

The mechanical behavior of printed circuit assemblies (PCA) at high strain rates is very important for the reliability of products used in harsh environments. The transition to Pb-free materials in the general electronics industry significantly impacts the mechanical reliability of solder joint interconnects,as widely recognized by the consumer electronics industry. Numerous mechanical behavior studies using a drop test have been reported on ball grid array components with different Pbfree solders. This study is focused on leaded and leadless components in comparison with ball grid array components assembled with Pb-free solder on medium complexity boards. This study is part of a large scale NASA DoD project and
utilized the same board design,assembly,and rework processes of that larger project. Components were attached to the boards using Pb-free solder SAC305. The TSOP-50,TQFP-144,QFN-20,and CLCC-20 components were then hand reworked using conventional SnPb solder to address the sustainment issue. Both 1x and 2x reworks were performed on the non-BGA devices. The PDIP components were also reworked; however,their analysis is not covered in this paper.
In the present work,a board-level drop shock test was performed on nine assemblies,each with 63 components attached. Each board was monitored for shock response and net electrical resistance for all components. In addition,three of these cards were monitored for board surface strain. The assemblies were fixtured to a drop table 3-up and subjected to either 340G or 500G shocks,for a total of 20 drops per board. The shock response,net resistance and strain were recorded in-situ during each drop. The vast majority of the electrical failures occurred on the PBGAs,which were not reworked in this study. Only three of the leaded and leadless components experienced electrical failure.
Damage from the drop shock test was assessed by examining electrically failed and non-failed non-BGA parts by dye-and-pry
and cross-section analyses followed by microstructural examination and defect mapping. It was found that the predominant failure mechanism was board side pad cratering. The cracks propagated through the board material between the laminate and glass fiber under the pad. Electrical failure was only observed when the Cu trace was broken. Of the leaded components that were electrically functional after drop testing,approximately one third were found to be mechanically damaged with pad cratering after dye and pry inspection. This hidden damage may be a reliability concern depending on the field use conditions. Only three leaded components electrically failed,two that were reworked with SnPb solder and one that was not reworked and contained the original SAC 305 solder. Of the two reworked joints that failed electrically,only the TQFP-144,the more compliant leaded component,showed signs of SnPb solder joint fatigue fracture. The failure of the other two components was due to pad cratering and severed traces. There was no correlation found between the number of reworks and the amount of electrical or mechanical failure since only three non-BGA components failed in the test. Most
importantly,this sample set showed no difference in drop test performance between SnPb-reworked and non-reworked Pb-free
solder joints for non-BGA components. More data will be available upon completion of the NASA DoD Pb-free project.