The use of electrodeposited copper for filling blind microvias has grown rapidly to become an essential and widely adopted
process used by various Printed Circuit Board (PCB) and package substrate manufacturers. Driven by the need for increased
speed,portability and wiring density,the interconnect pitch on both semiconductor packages and High Density Interconnect
(HDI) substrates continue to shrink. As these designs evolve and dimensions shrink,the ability of copper filling process to
consistently produce void free copper filled microvias comes under increasing pressure.
This paper describes a new pattern-plate,Direct Current (DC) copper electroplating process designed for HDI and packaging
substrate applications. Process performance as a function of processing variables is discussed.

This paper presents a novel electrolytic copper panel plate system incorporating equipment and specially developed electrolyte which enables filling of blind micro vias with a minimum of surface plated copper.
The system utilises Uniplate plating equipment which may be combined into a wet to wet metallisation and copper plating line. The InPulse2 electrolytic copper plating module uses insoluble anodes for uniform plating conditions together with a special clamping system for electrical contact to the substrate which also enables production of material with thin copper foil down to 3 µm. Such material is becoming more common in HDI production but requires special techniques to ensure optimum surface distribution at high production current densities. The insoluble anodes are segmented and each anode segment has an individually controlled rectifier to ensure uniform blind micro via filling over the whole substrate.
Blind micro vias typically seen in hand held devices with 70 µm depth and 100 µm diameter can be easily filled with this system with only 15 µm copper deposited on the surface,this offers the possibility to meet the requirement for 2 MIL line and space with panel plating techniques. Also due to the low thickness of plated copper,savings in materials are very significant particularly in copper metal but also in solder mask and etching chemistry. This process has already reached a high acceptance in the mass production of HDI circuit boards particularly for hand held devices.
Development results showing the system capability also for through hole filling of substrates is shown together with discussion of possible application areas for this new technology.

The plated thru hole has changed considerably in 50 years of electronic packaging,but in its many forms remains the most
common interconnection in 1st and 2nd level electronic packaging,and is still one of the most feared in terms of reliability. The transition from the original solder filled holes to BGA wiring vias,subcomposite buried vias,and today’s microvias has resulted in many new failure mechanisms,not only in the copper interconnections but also in the surrounding laminate,especially with Pb free reflows.
This presentation surveys the most significant via and via-related laminate failure mechanisms from past to present using data from current induced thermal cycling (CITC) testing,failure analysis,and other sources. The relative life and failure modes of thru vias,buried vias,and microvias (stacked vs. non-stacked) are compared,along with the affect of structure,materials,and peak temperatures on the above. The origin of via-induced laminate failures such as “eyebrow cracks” and Pb free related internal delamination is also explored. Video clips of laminate coupons during Pb free reflows are shown,including examples of failure mechanisms as they occur,to vividly illustrate the challenges involved and to help reveal the root causes. Finally,an extrapolation to future technology trends for laminate substrates is attempted to address the question—what might be the failure modes of tomorrow,and will via/laminate reliability be better or worse?

European legislation has meant that lead-free solders now dominate mainstream electronics manufacturing. These
replacement solders are all high tin alloys with significantly higher melting points compared to conventional tin-lead materials. Substrate technology has been developed around reinforced resin materials and concerns have been raised regarding the increased degradation caused by the associated higher processing temperatures. This is compounded by the interconnecting structures being brought into closer proximity as a result of increasing technology advances driven by miniaturisation. The removal of non-functional pads to facilitate signal routing and improved drilling conditions for high aspect ratio vias,may also affect substrate reliability.
The National Physical Laboratory and PWB Interconnect Solutions Inc. have undertaken a joint study following identical test structures through both thermal cycling,with constant electrical monitoring (event detecting) and Interconnect Stress Testing (IST). The test vehicles included patterns to monitor changes in interconnection spacing (pitch) and also the effect of removing non-functional pads. The failure modes generated with both techniques were similar as were the relative rankings of the effects. The results showed that the removal of non-functional pads tended to improve reliability for high aspect ratio plated through holes in thicker substrates,although increasing interconnection pitch had little effect on failure rate.
The results generated by both thermal cycling and IST showed extremely good correlation. Failures occurred at a slightly lower number of cycles for IST compared to thermal cycling due to the unique ability of a more stringent failure criterion possible with IST. The relative ranking of the level of failures is identical for both the thermal cycling and IST but the results were obtained in very different timescales. IST has been shown to give a fast comparable result to thermal cycle testing with constant monitoring,but thermal cycling may be more beneficial if a wider range of experimental parameters (E.g. Solder joints) are to be tested simultaneously.

Reliability testing of printed wire boards (PWBs) by thermal cycling offers the ability to compare relative survivability through assembly and reliability in the end use environment. This article delineates an eleven step method to establish a test protocol that will maximize accuracy,applicability and reduced costs and reduce the propensity for confounded data in thermal cycle testing of bare PWBs exposed to lead-free assembly and rework simulation. The method presented in this paper is targeted to the unique challenges afforded by lead-free testing applications and testing of the integrity of conductive interconnections and dielectric materials.

Though the electronics industry is nearing the 3-year anniversary marking the ban of lead from electronics products,several
challenges still remain with existing lead-free materials for certain applications. The commonly used and accepted SnAgCu
(tin-silver-copper,also known as SAC) alloy has proven to be a suitable material for the production of many devices but,for
those applications that require extremely high reliability,current SAC materials are less than ideal. In particular,devices that
will find end use in automotive and military/aerospace products require a lead-free material that can withstand the higher
temperatures operation life (e.g. automotive under-the-hood conditions),offer vibration resistance not commonly associated
with traditional SAC alloys and deliver high temperature (> 125oC) thermal cycling reliability levels beyond those available
with current commercialized SAC materials.

This paper discusses the results of several independent experiments designed to address the many aspects of successful PoP integration. Assembly through the use of in-line stacking and pre-stacking was evaluated. Top package soldering was
performed by dipping in either flux or paste. The warpage behavior of each level,as well as the full module was characterized through simulated reflow using Shadow-Moiré analysis. Warpage behavior was found to be a limiting factor in assembly yields.
Reliability of PoP assemblies was evaluated using drop/shock,vibration and thermal cycling. The level at which failure occurred depended on the location of the module on the PCB. Underfill was found to greatly enhance mechanical reliability,however thermal cycling reliability was decreased.

For decades the manufacturers of electronic components have furnished products that were most compatible with soldering
processes that employed a eutectic alloy composition that contained tin and lead. In recent years the European Union (EU)
developed the 'Restriction of Hazardous Substances' (RoHS) directive that forced the global electronics industry supply chain
to modify their materials and processes to accommodate lead-free soldering. Component suppliers responded by furnishing
lead-free alloy terminal plating. To accommodate the lead-free components,board suppliers developed a number of lead-free
surface finishes and coatings. The circuit boards base material has required change as well to meet the requirements of higher
temperature lead-free soldering processes needed for assembly.
Although most of the companies supplying finished electronic products to consumers in North America are not required by
legislation to comply with the EU directive,many are being forced to modify their assembly process because some of the alloys plated on the lead-free components and printed circuit boards are not really compatible with lead-bearing solder materials. The other issue is the components and boards originally developed for eutectic soldering can not be used in a leadfree process due primarily to the mold compounds and base materials lack of capability to hold up at the elevated temperatures required for lead-free soldering. In this paper the author will address three key issues a designer will need to consider during the planning phase of a new products development; Component selection for lead-free applications,Product exemption criteria and Specifying compatible PCB material and finish.

The trend towards increasingly complex designs with smaller physical sizes has been translated into ever-increasing pressure on system developers to pack more functions and options into a given area. In addition,cost needs to be driven down as much as possible. As a result,the design process has become more extensive in terms of resources,complexity,choice of PCB technology and cost reduction. In order to handle this challenge effectively,one would like to predict the efforts involved in the layout design a-priori. This capability is now available in the form of “Predictability Calculator”,described below.
The Predictability Calculator is a tool that provides the designer with the necessary trade-off analysis performed at the feasibility stage,given the constraints of the assigned area. It takes advantage of the fact that all designs are done today using CAD systems,hence data analysis is possible given the electrical schematics that is available at an early stage of the PCB layout design. This initial data include the number of components and their type and characteristics that are known once they have been selected. The number of connections is also available based on the interconnections and busses.
Although it is recognized that the PCB technology may be selected independently of the designer,it is nonetheless a part of the tradeoffs supplied by the Predictability Calculator with the objective of providing maximum performance at a minimal cost.
This tool has been utilized so far in the feasibility stage of over 40 complex boards,and also in post mortem analysis of other boards. It has thus demonstrated a proven capability of providing feasibility data for the routing complexity with a high level of confidence. The next step in the tool development will include an in-depth placement feasibility and the trade offs with embedded resistors and capacitors.

As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC,at the IC package,at the module,at the hybrid,the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability,although the development of fine-pitch substrates and assembly technology has
narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process.
This paper provides a comparison of different commonly used technologies including flip-chip,chip-size and wafer level array package methodologies detailed in a new publication,IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format,the impact on current component characteristics and reviews the appropriate PCB design guidelines to ensure efficient assembly processing. The focus of the IPC document is to provide useful and practical information to those who are considering the adoption of bare die or die size array
components.