Conformal coatings are used in high reliability electronics to protect the circuits from environmental contaminants. They are
applied by a variety of methods,and in varying thicknesses. Confirming that the thickness meets specifications called out by
documentation or customer can be problematic. Mechanical,ultrasonic,electrical (capacitive,eddy current),and various optical techniques are available,but all involve incurring significant limitations/penalties in capability,capacity or cost.
For optically transparent,and some translucent coatings,it is possible to accurately measure the thickness using optical (focal) techniques. This paper presents data on an innovative coating measurement process based on commercially-available low-cost optical equipment modified to make the measurements. The modified equipment is capable of making measurements on films as thin as 25µm (0.001”) and thicker than 1000µm (0.040”) with high repeatability. The method does not require a free edge and is not dependent on before/after coating differential measurement. The process has been fully developed and is used in a production environment.
The paper presents an overview of the equipment and method,Gage R&R data for the process,as well as comparative
information on other available techniques. The focal technique is applicable to measurement of all types of optically clear coatings and films,and is appropriate for moderate-volume measurement applications where direct,non-contact measurement of coated parts is desirable and where measurement in small areas is required.

During lead-free wave soldering or rework operation for through hole components,high rate copper dissolution may occur to printed wiring boards. It is widely believed that Sn-Ag-Cu (SAC) lead-free alloys,the currently most popular alloys in the electronic industry,have more than twice the rate of copper dissolution compared to the Sn-Pb eutectic (63Sn-37Pb) solder alloy. In this study,copper dissolution was evaluated with four lead-free alloys (SAC305,K100LD,SC995e,SN100C) at temperatures 245,260,280 and 300oC with time duration of 20,60,300 and 600 seconds. Results show that K100LD and SN100C have the lowest rate of copper dissolution. A unique dynamic copper dissolution testing was also performed to investigate effects of liquid solder dynamic flow speed,time and temperature on dissolution kinetics. These dynamic tests involved three different sample motion speeds of 2,5 and 15 ft/min at temperatures of 245,260 and 280oC with time duration of 20,60 and 300 seconds. Our unique test setup clearly demonstrated that alloy selection and process window definition are critical for lead-free soldering for through hole component assembly and repair operation.

Hot gas rework of BGAs with a mirrored BGA design configuration using SnAgCu based lead-free alloys is more challenging as compared to conventional SnPb techniques. Rework of BGAs using a conventional SnPb alloy system has historically required that mirrored BGA solder joints remain below the eutectic melt temperature of 183?C to avoid secondary (or partial) reflow of these mirrored solder joints. This requirement was traditionally established to maximize second level solder joint reliability performance of mirrored BGA devices. However,with the migration to SnAgCu based alloys,the approach of ensuring that mirrored BGA device solder joints also remain below the SnAgCu melting point (217?C) during hot gas rework operations presents a more difficult challenge. Increased conductive heat transfer rates through the printed circuit board (PCB) along with increased thermal exposures to adjacent surface mount components are impacts of elevated processing temperatures associated with the use of lead-free solders. As a result,secondary reflow of mirrored BGA solder joints is sometimes unavoidable – especially for thin PCB cross sections,ranging nominally from 0.050” to 0.062” (1.2 to 1.6mm).
The intent of this paper is to recommend changes in assembly materials and the process itself during hot gas rework of lead-free BGAs with a mirrored BGA configuration. The metallurgical analysis of final solder joint structures and the reliability performance of fully reflowed mirrored BGA devices will be reported. An eight month development effort indicates that mirrored SnAgCu BGA solder joints should be allowed to fully reflow when it is not possible to prevent mirrored solder joints from reaching onset melting (pasty range) temperatures. Thermo-mechanical solder joint reliability has shown improvement when these joints are processed above the alloy pasty range; when all attempts to remain below this range have been exhausted.

An experimental study was conducted to examine the impact of rework processes on quality and reliability. In this study,676 IO plastic ball grid array packages were assembled with Sn3.0Ag0.5Cu solder paste and eutectic SnPb solder paste. Selected parts on circuit boards were subjected to rework processes one time,three times and five times. X-ray inspection and environmental scanning electron microscope were used to investigate impact of part replacement on the ball grid array voids,the microstructure of intermetallic compound,and copper pads. Since the rework process includes multiple liquid solder state periods,it consumes more copper and makes the intermetallic compound growth trend an interesting topic. Copper pad dissolution was found in the samples after multiple rework processes. Lead-free assemblies consumed more copper than mixed assemblies because of higher concentration of Sn in lead-free solder. The thickness of intermetallic layer increased as the total rework time increased. Ultra thick intermetallic compound was found at the connection area between the copper pad and the copper trace after the rework processes were applied three times and five times,which may lead to reliability concerns.

The New England Lead Free Consortium,composed of many companies in the electronic supply chain in the regional area and chaired by the author; has embarked on an extensive long term reliability study of lead-free and halogen free electronic assemblies. Specialized PCB’s were built,assembled and reworked at the consortium member companies using multiple types of laminates,PCB surface finishes and various component types including through-hole and surface mount technology. The assemblies were examined for visual characteristics and subsequently tested for reliability using temperature cycling as well as vibration testing. All rework,reliability tests,and evaluations have used or will be using industry standards,methods and techniques for easy reference to other long term reliability studies. The studies will include comparison to a baseline of leaded electronic assemblies. This paper will outline results obtained so far into the long term reliability study.

The reliability of lead-free (LF) solder joints in surface-mounted device components (SMD) has been investigated after thermo-cycle testing. Kirkendall voids have been observed at the interface component/solder together with the formation of fractures. The evolution,the morphology and the elemental analysis of the intermetallic layer have been evaluated before and after the thermal treatment. Voids produced by the release of volatile species during the soldering process due to the application of flux were present. If compared with SnPb soldered systems,lead-free joints are characterized by larger and a higher amount of voids. In several electronic joints (ball grid arrays (BGA),surface-mounted device components (SMD),etc.) fractures developed after the thermal stresses generated during the accelerated thermal aging. Warpage of the PCB has also been observed. Backward and forward compatibility of SnPb and lead-free BGA connections has been performed on pads with an ENIG finish. The effect of the reflow peak temperature on the structure of the intermetallic layer has been assessed.

The High Density Packaging Users Group (HDPUG) consortia completed an extensive study of 29 different bare board material and stackup combinations and their associated performance after 6X Pb-free reflow at 260C. Data presented will focus on the air-air thermal cycling,IST testing and material survivability after Pb-free assembly reflow portions of this testing. Test board design aspects,manufacturing processes,Weibull analysis,and failure analysis data will be presented. The impact of plated through hole pitch on laminate integrity and how material properties relate to the results will be discussed.

The signal channels that link high speed processors to memory and various other peripherals,are limited by the inherent characteristics of the printed circuit board. These are what ultimately connect information to the outside world. One limiting factor is the effect of non-uniformity of the glass fiber distribution in the printed circuit substrate material,also known as fiber weave effect (FWE). FWE introduces signal skew and timing errors which place an upper limit on bit rate and trace length.
Using unique fabrication techniques and a proprietary low dielectric constant glass composition,a revolutionary glass fabric is presented that is essentially free of fiber weave effect while demonstrating inherently improved resistance to conductive
anodic filament (CAF) formation. Improved laminate performance is demonstrated with finite element modeling and HyperLynx simulations,and corroborated with dielectric property measurements on prototype substrates.
A printed circuit board using this material demonstrates superior signal integrity performance over the traditional glass-based
solution. By uniformly distributing glass fibers the maximum surface area becomes available to bond with the resin,which is
enhanced by direct application of a finish to provide a high quality interface between glass and resin. Two high profile performance issues,fiber weave effect and CAF,are addressed by a unique laminate reinforcement.

Over the years,signal integrity performance and bandwidth gets more critical for today’s higher signal transmission speeds and bandwidth demand in every field of applications such as computing,multimedia,communication infrastructure and a variety of communication bus and cable like PCI express,SATA II and AGP bus for computer system. Base material electrical performance especially for dielectric loss will dominate signal communication behavior while communication speeds push up to 5~10Gbps.
Because one labors under the hypothesis of lead-free process compatibility,high Tg demand and thermal reliability concerns,the base resin system candidates for print circuit boards is limited. Basically,bisphenol-A novolac construction resin has been the mainstream resin in the market for years. Unfortunately,its characteristic restricts its dielectric loss performance . How can one further improve dielectric loss and signal integrity performance? Besides post-remedial measures in manufacturing technology like oxide treatment roughness,laminate construction,resin content,fabric weaving density,etc.,CCL resin system reactivity and the choice of catalyst system are two significant factors for electrical performance improvement beside the resin and hardener design. Our study shows that a resin system reactivity with and without optimization can make a difference of up to 20% gap in signal integrity performance.

Copper Wrap Plate as specified in IPC 6012B table 3-2,is a requirement developed to enhance reliability for PCB’s designed with via structures that require planarization and surface capping. PCB’s built without wrap plating are more prone to failures associated with separation between the interconnection of the barrel copper to the surface copper. The improvement in reliability is a function of the copper wrap thickness,which supports the difference in IPC requirements for Class II and Class III programs. The general rule is “the thicker the wrap plating the better the reliability.” The increase in copper thickness,associated with wrap plating,however competes with the ability for PCB fabricators to manufacture products with high density and fine features. The general rule for manufacturing fine features is “the thinner the copper the better the manufacturability.”
The technology developed by DDI Corp. called FLAT-WRAP™ offers a copper wrap solution that does not require build-up of copper on the external surface of a filled plated hole. This allows the improvement in reliability without sacrificing the ability to manufacture designs with high density and/or fine features. This technology also facilitates,in process non-destructive copper thickness measurements and ensures consistency of copper wrap thickness across the entire board surface. In this technology,the external surface copper thickness of filled plated holes will control the copper wrap thickness. In Printed Circuit Board designs requiring multiple copper wraps,the benefits of this technology are even more evident.
This article examines the current process problems with copper wrap plate and discusses the benefits provided by the new technology with respect to manufacturing and reliability.