An important criterion for dielectric materials used in the microelectronics industry is their flammability. Typically,flame
retardant epoxy resins use bromine-containing flame-retardants. In the electronics industry,non-halogen flame-retardants are
becoming increasing popular due to environmental pressures in the marketplace and in response to recent regulatory issues. However,there is a perception that halogen-free flame retarded systems are more costly and can have performance issues. For example,phosphorus flame-retardants can be expensive and require high dosages,which can have an adverse effect on some properties. For these reasons,new,more cost effective systems with minimum effect of performance properties are desired. Lowering the needed dosage of flame retardant can have lower cost implications and concurrent improvement in properties. Our approach to lowering the required flame retardant dosage was to react low molecular weight of poly (2,6-dimethyl-1,4-phenylene ether),PPE,macromonomer with epoxy resins. The highly aromatic PPE structure exhibits inherent resistance to burning. Indeed,a unique feature of PPE blends and alloys are their ease of flame retarding with phosphorusbased flame-retardants. Therefore,the reaction of PPE macromonomer with epoxy resins offers the intriguing potential of lowering the needed dosage of flame-retardant. For example,the use of 30 and 50-wt% PPE macromer in epoxy resin resulted in a 25-60% reduction in phosphorus-based flame retardant needed for V-0 flame performance. This in turn
improves the odds that physical and mechanical properties of the laminate are not negatively impacted by the flame retardant.
Indeed,the use of PPE macromer in halogen-free FR epoxy resins resulted in a single phase networks with increased toughness,lower dielectric properties,lower moisture absorption,and high glass transition temperatures (Tgs).

The mobile communication devices such as cell phones require high speed transmission of large volume data as well as reduction in size and weight. When signal is transmitted in high speed and frequency on PCB,signal integrity becomes a problem. This problem is getting worse as the transmission becomes faster and larger. Therefore,materials with low Dk/Df are need for high frequency board.
Another requirement for current communication board is environmental friendliness,which is lead and halogen free. As for
laminates,there are some low Dk/Df ones and many halogen free ones. However,material with both is hard to find,quite expensive and difficult to process. Therefore,communication industry is looking for new materials. To meet this demand,a novel halogen free material with low Dk/Df,DS-7402D,has been developed. A hydrophobic epoxy resin was used as base resin to improve the dielectric properties. In addition,a phosphorus containing resin was applied as a hardener and halogen free flame retardant. The resulting material has better dielectric properties,Dk of 3.9 and Df of 0.01,than those of conventional FR-4. It also shows an excellent thermal stability,Td higher than 380C,which makes it suitable for lead-free process. The other properties of this material,such as copper adhesion,modulus and water absorption will be presented.

The electronics industry continues to strive to provide more environmentally friendly products. This movement is partly due to legislation from various countries,partly due to public outcry from well publicized 3rd world recycling practices,and partly due to non-government organizations (NGOs) testing and publishing information on electronic devices regarding their content of various toxic materials. One set of materials targeted for reduction and eventual elimination are halogenated compounds. Halogens are found in plastics for cables and housings,board laminate materials,components,and soldering fluxes. Replacing these halogenated compounds can have a dramatic affect on the PCB assembly process. In this paper those challenges will be discussed as well as techniques and practices that will help ensure high end of line yields and continued reliability.

One of the solder joint failures encountered frequently during Printed Circuit Board Assembly (PCBA) is due to Head-in-Pillow (HiP) defects. The primary cause of HiP defect is due to the warpage of the component during the reflow process. The ultimate solution for solving HiP is to eliminate component warpage however that is very difficult to accomplish in all packages due to various material and construction constraints. Hence,there is a need to find other approaches to solve this problem. One effective solution would be to investigate a solder paste that can mitigate HiP defects.
The theory investigated here presumes that had the BGA spheres maintain contact with the main card solder paste the HiP defect would not occur. Therefore it is during SMT reflow that package warpage raises the BGA sphere(s) up off the applied solder during flux activation and reflow. The BGA sphere only returns to contact the melted/coalesces solder paste during cooling when the package has begun to return to its initial flatness. At this point either the flux is exhausted and is unable to form the joint or the flux itself has created barrier between the two solder features,BGA sphere and PCB solder bump created from the reflow paste on pad.
The Head-in-Pillow defects parts per million (DPPM) level would require a DOE sample size in the thousands therefore this study devised a method to create Head-in-Pillow defect in a controlled lab environment. This method eliminates the use of expensive problematic BGA components and instead applies control over reflow conditions and timing of the contact between the solder ball and the melted solder paste. The SRT BGA rework machine was used to effect programmable control of the time and temperature profile and sphere contact timing.
A baseline SRT process was established using a solder paste common to multiply production line exhibiting HiP defects. The baseline profile was modified until the baseline solder paste consistently created HiP defects. Using these same programmed SRT parameters eight other no-clean solder pastes from different vendors were evaluated. A high resolution video camera was used to record the entire reflow process and track the occurrence of the HiP joint. The performances of all the pastes were analyzed to determine the best solder paste to mitigate HiP defects. The results of this study were incorporated into production and were further validated through the elimination of the HiP joint defect. This test method provides engineers a means to evaluate a solder paste effectiveness in mitigating HiP defects.

The head on pillow defect is becoming more common. This paper describes one such occurrence for an OEM and explains how it was dealt with. In this particular case it was solved by application of problem solving skills by the OEM,component supplier and the solder paste provider.

The widely publicized and studied implementation of lead free solders has led to increased scrutiny on the solder joint formation for surface mount technology electronic components. During the lead free transition packaging technology for power semiconductor components increasingly embraced molded leaded package (MLP) technology. Due to the application demands of power devices,namely temperature control and reliability,many end users have placed considerable emphasis on process void minimization. Experiments have shown that increasing the quantity of solder paste printed will often minimize process voiding,but incidences of solder balling and beading often increase. Due to their comparative complexity,multi-die MLPs have shown to be more sensitive to solder process design and control. This created the need for a thorough investigation of solder process parameters,and a method to collect and analyze the data from a set of experiments to optimize the process. No previous process found by the experimenters was found to meet the needs of the problem.
Demonstrated in this paper is a six sigma based methodology for developing a rigorous design of experiments for determining the best process for surface mounting a 6x6 DrMOS MLP component. Critical factors will be identified and treated statistically using DMAIC methods.

Doing more with less has been the standard operating procedure in manufacturing over the past ten years. Everyone is looking for areas where they can cut corners,maintain quality,and improve productivity. Many placement machines have the ability to self-calibrate and provide capability numbers. In an attempt to save resources,many manufacturers are using these values in place of true capability studies. This practice prompts two questions that need to be answered: “How valid is the internal measurement?” and “If it is not valid,is there still value in using it?” The simple answer to these questions is that internal calibrations are not valid to predict yield,but do have value for the user. This paper compares and contrasts acquiring a Cpk value from an external metrology system versus one from an internal system. It also provides evidence that an external system is necessary to run a true lean six sigma facility.
An external metrology system provides the capability to truly reduce the cost of poor quality and increase profits. Included case studies show the improvements a user will see in metrics like DPMO and first pass yield when using an external metrology system versus only using an internal calibration system. These studies also show how improving DPMO and first pass yield will actually reduce manufacturing costs.. Increased profitability is what all factories are trying to achieve,but it can be diminished due to potentially misleading reports provided by internal calibration systems. In many companies the cost of this mistake is unknown to management— consequently perpetuating with every new production run.

Under cycling loading conditions,solder joints are susceptible to fatigue cracking,which often initiates at the surface where the strain range is maximized. Event detectors have been widely used to detect failure of solder joints during reliability testing. These devices monitor DC resistance using very high sampling rates,thus allowing failure to be defined on the basis of a minimum number of samples that exceed a failure threshold. Event detectors excel at recording rapid,intermittent changes in resistance and identifying a DC open circuit,which is the typical criterion for failure. However,event detectors are not sensitive to early stages of degradation,because changes in resistance under cyclic loading conditions do not occur until a crack has propagated almost all the way through a solder joint,and because their sensitivity to small changes in DC
resistance is adversely affected by temperature variations and electromagnetic interference.
RF impedance monitoring offers a highly sensitive means of detecting interconnect degradation. Due to the skin effect,a
phenomenon wherein signal propagation at high frequencies is concentrated near the surface of a conductor,even a small crack initiating at the surface of a solder joint raises the RF impedance. Thus,RF impedance monitoring can detect early stages of solder joint degradation long before it results in a DC open circuit. In order to compare the respective sensitivities in detecting solder joint degradation between RF impedance and event detectors,mechanical fatigue tests have been conducted with an impedance-controlled circuit board on which a surface mount component was soldered. During cyclic loading,simultaneous measurements were taken of DC resistance and the reflection coefficients obtained from time domain reflectometry (TDR) as a measure of RF impedance. The TDR reflection coefficients were consistently observed to increase in response to early stages of solder joint cracking prior to the first failure detection of an event detector. The results demonstrate that RF impedance monitoring has the potential to predict and prevent failures of electronic products due to solder joint cracking by providing a warning that an interconnect has begun to degrade.

Most electronic assemblies comprise a number of chips,packages and similar components that are attached to Printed Circuit Boards (PCBs) or similar substrates,usually using solder joints. Also most frequently,the components and the substrates are made of materials that have different Thermal Coefficients of Expansion. If such assemblies get exposed to harsh environments,such as severe thermal cycling,or to frequent power cycling,then they run the risk of having their solder joints stressed,and in some cases,the stresses can reach a level where some joints would fail. This is especially true,when the components are relatively large in size,like half an inch square or larger,and when the temperature variations are fairly large. It is well known that if the solder joints are tall,like columns,stretching between the components and the substrate,like the Solder Column(s) with Copper Tape,then the induced stresses in the joints are reduced and the assemblies can more readily survive such harsh conditions. This paper discloses some additional novel features,which enhance the performance of such column-like joints,which make such joints even better than traditional columns,and enhance the reliability and extend the
operating life of such electronic assemblies. The columns in this case have an elongated cross section,and are oriented in a way that presents the lowest resistance to flexing in the direction of the thermal deformation of the assembled components. The concepts have been applied also to leaded components,by orienting their leads. The paper describes a number of such design concepts and embodiments. Some of them are already patented,while others are still patent pending.

Future handheld electronic products will be slimmer than today and deliver more functions,enabled by innovative electronics
packaging design using smaller components with greater I/Os assembled in higher density. As solder interconnects between
component and circuit board shorten,they also become weaker. This causes us greater concern on the survivability of such delicate electronic interconnects under normal handling impacts and serves motivation for formal study. This investigation will evaluate the influence of stencil printed solder volume on CVBGA97 electronic component lifetime in mechanical stress testing. A stencil aperture design to print a lower limit of solder paste volume has been thoroughly characterized as the first step towards determining the range of print volumes exhibiting the greatest influence on drop,bend,and die shear test performance. In this printing focused piece of work,print volume measurements were found varied across different circuit board pad designs with no change in aperture size. Highest paste volume transfer consistently occurred with solder mask defined pads. Stencil aperture and circuit board pad design variables are discussed in detail.