As the requirements for controlled depth micro-vias become ever increasing in today’s market place the best feasible solution
appears to be laser drilling. However laser drilling can be problematic when approaching dielectric thicknesses over 3 mils. FR4 is a composite of epoxy and fiberglass with the fiberglass portion being most problematic for the laser. Since the fiberglass is a weave the laser will have to be adjusted to drill through the knuckle of the glass intersect and hit the capture pad. This is achievable however lateral ablation of the epoxy can occur. This phenomenon can lead to uneven plating and potential reliability issues as can be seen in Figure 1.

As more power is driven through active devices,the integrity of materials used to make the electrically conductive interfaces is becoming ever more critical to the performance of RF radar systems. A variety of technologies including thermal grease,solder and adhesive materials have been used to achieve this interface. In many applications,the use of conductive film adhesives are employed to take advantage of key benefits of the materials such as consistent and uniform bondline control,high electrical conductivity,and lower processing temperatures. This paper will compare the performance of an electrically conductive film adhesive widely used over the last twenty years in the electronics industry with that of a newly developed film designed to provide greater resistance to environmental exposure.

Great efforts are expended by researchers to develop new and better thermal interface materials. In contrast,optimization of the performance of a given material is usually left to more empirical efforts. Unfortunately,interactions between the many parameters affecting performance make the design of experiments required for empirical optimization impractically large. We are conducting systematic mechanistic studies on the combined effects of materials selection and process parameters such as normal forces,assembly speeds,and thermal profiles on bondline macro/microstructure and thermal performance.
The most common type of medium/high-performance thermal interface material is undoubtedly that of polymers filled with
conductive particles,most often Ag. However,these materials rarely perform as well in a practical application as predicted based on manufacturer supplied data sheets. This is usually ascribed to defects such as voids,porosity and filler distribution heterogeneity. Such defects can be minimized by process optimization,but we also believe that we can learn to tailor some level of heterogeneity to our advantage. In fact,a thermal resistance two and a half times lower than that predicted based on the data sheet has already been demonstrated for one high-end commercial material. Moreover,this can be compatible with a practical manufacturing process.
The present paper offers a discussion of results of systematic process studies on commercial filled polymer materials,including correlations between process parameters,defects and final bondline thickness. Important insights were derived from a new technique allowing the in-situ measurement of bondline electrical resistance during processing. The indication is that the dominant pathways for heat transport are provided by chains of Ag particles in good electrical contact with each other. However,typical thermal conductivities of adhesives with,say,30% Ag (by volume) are lower than that of pure Ag by a factor of fifty or more. The reason for this is that a relatively small fraction of the Ag particles are in conducting chains; in many instances heat must travel through interfaces between the Ag and thin coatings or layers of polymer. Indications are that the fraction of metallic (electron) transport (transport through chains of Ag) can be enhanced in an optimized assembly process.

Ideas,manufacturing processes,materials and components that were in the realm of science fiction a few years ago are now being adopted into mainstream PCB products. Devices are getting smaller,boards are getting denser,and parts are getting more complex. Array packages are becoming more popular. On the near horizon we see the popularity of high density interconnect rising. Solder Jet printing and cold attachment rival traditional solder printing. Manufacturers are building smaller and smaller quantities – even batches of one! What does this all mean for traditional Automated Optical Inspection (AOI),which grew up in a world of technologies that might be superseded soon? In this paper,we discuss the strengths and weaknesses of AOI given these significant changes in PCB materials and manufacturing methods. We also examine alternative inspection methodologies that may complement or replace AOI.

Prediction of accurate values for insertion loss (S21) on printed circuit boards has become ever more critical to SI modeling as signal speeds required for next-generation networking equipment move into the 10+ GHz range. Existing industry-standard insertion loss estimation techniques assume that the copper conductors (PCB traces) are smooth,when in fact they are not. The error thus induced is less significant at lower speeds,but cannot be ignored at frequencies above a few GHz. Accurate estimation of PCB laminate dissipation factor (Df) is another goal integral to SI modeling. Industry-standard methods again assume the smooth copper case,with consequent frequency-dependent error introduced into extracted values of Df. This paper describes a set of stripline PCB test vehicles used to correlate copper trace surface roughness to insertion loss. The main errors induced in extracted values of Df resulting from increased conductor losses due to surface roughness have been analyzed.

The Quad Flat Pack No Leads (QFN) type of leadless package,also known as Land Grid Array (LGA),is rapidly increasing in use for wireless,automotive,telecom and many other areas because of its low cost,low stand-off height and excellent thermal and electrical properties. The implementation of any new package type always results in a learning curve for its use in design and processing,especially for the Process and Quality Engineers who have to get to grips with the challenges that these packages bring. In particular,the central termination of these QFN packages are prone,in most practical experience,to exhibit a high,or even excessive,level of voiding when seen under x-ray inspection. Such excessive voiding can not only affect the package?s thermal performance during operation,but it can also increase the stand-off height from the board making the QFN float higher on the solder surface. Such action can apply stresses to the device outer terminations causing them to no longer remain planar and affect joint quality. Therefore,monitoring central termination voiding provides a valuable method to qualify the presence of unsuitable stand-off heights which,in turn,may increase the propensity for open joints during production.
This paper will discuss the results of experiments being undertaken on identical QFN devices where the quantity of solder under the central termination was varied and the ensuing voiding level calculated by x-ray inspection. The results will be discussed in line with correlating this data as a method to provide a suggested upper limit for QFN central termination voiding so as to minimise the possibility of open joints in production.

Stencil printing is a critical first step in surface mount assembly. It is often cited that the solder paste printing operation causes about 50%-80% of the defects found in the assembly of PCBs. Printing is widely recognized as a complex process whose optimal performance depends on the adjustment of a substantial number of parameters. It is not uncommon to hear that stencil printing is more of an art than science. In fact,the process is so complex that sub-optimal print parameters usually end up being used. In addition,stencil printing produces relatively noisy data,which makes the print process extremely difficult to control. Minimizing the variance of the deposited location and volumes will improve the quality of the process and produce more reliable solder joints.
In an effort to improve the performance of stencil printers,continuous process monitoring and statistical process control
techniques have traditionally been used. However,these techniques require constant process tweaking and highly depend on process expertise. Presently,manufacturing engineers tune control parameters to a recommended nominal value suggested by
the equipment and/or solder paste manufacturers. In general,line engineers optimize control parameters by printing a few initial boards and hope that the process stays in control. However,when a process disturbance or drift occurs,the yield of the process typically degrades rapidly to the point of becoming unacceptable.
In general,there are two critical aspects to a printing process. You want to put down the right volume of paste on the right spot. In another word,we not only have to monitor the amount of paste volume we also need to monitor X,Y and ? registration of the board. This issue is compounded when dealing with miniature components such as 0201,01005,0.4 mm and 0.3 mm CSP’s and lead free paste. Lead-free paste is known to have less spread,or wet-ability,and adds to the challenge.
To improve the performance of the solder paste printing process we have identified several control schemes that can be developed into commercial products with no technical risks. These are automated print registration correction,automated stencil inspection coupled with stencil wiping and finally,advanced closed loop control consisting of print parameters adjustment (such as,squeegee speed) based on the 3D SPI volume,area and/or height measurements.
In this paper we present selected results from the first phase of this work focusing on print registration control,using a closed loop control scheme.

Thermo-gravimetric Analysis (TGA) measures weight changes in a material as a function of temperature (or time) under a controlled atmosphere. This technique is currently used in the design phase of lead-free solder paste. In this study,the same technique is used to predict how long solder paste can be left on the stencil before it dries out and is no longer suitable for further use.
In many SMT production lines,the solder paste lies exposed on the stencil for an extended period without being used. This can be due to many reasons: product change-over,machine downtime in the SMT line or just not enough production volume for the line to run continuously. Some chemistry in the paste slowly evaporates even at room temperature. This affects the rheological properties of the solder paste and may result in poor printing,or aperture clogging of the stencil.
Advanced TGA instruments have the ability to simulate a reflow process under different atmospheres. A solder paste can be
heated in nitrogen or air with different gas flow speeds over the sample. The TGA shows that the chemistry of a solder paste
responds differently when the atmospheric conditions change. Knowing this,an optimal heating profile under nitrogen may be different from one when soldering in air. Heating solder paste and determining its characteristics will help reduce the number of solder defects in SMT production.

Since the beginning of Surface Mount Technology over 40 years ago solder paste has been an integral element in electronics assembly. Historically solder paste design and development has been,in a sense,analog in nature. Some users have considered it “black magic”. Formulations were based on previous knowledge bases,honed over the years by tweaking and trial and error science. Paste testing followed suit with virtually all performance tests based on subjective expert inspection and critique. Although statistical design elements have been appending these development methods in recent years,complete digital paste design has been confounded by the lack of quantitative paste tests and the complexity of mixture design technology.
Today we can state that the digital solder paste has been developed by combining “Design for Six Sigma” techniques,quantitative testing methods for all major attributes and specific performance targets derived from a close customer interface. This paper will walk the process of creating this design system,beginning with the building and refining of the “House of Quality” and then coupling this with previously developed quantitative benchmarking techniques,testing and perfecting these techniques for statistical validity,pre-screening potential ingredients,running the mixture Design of Experiments (DOE) and finally verifying the formula. This system has yielded a comprehensive knowledge of interactions for every constituent in the formula,as well as statistically predicted the optimum formula based on desired properties and their relative importance.
There are many obvious benefits to the digital solder paste over its analog predecessors. The design outcome forms a mathematical basis for a chemical formula with the interactive effects on performance attributes for each constituent fully understood. This permits performance simulations of constituent changes,intuitive troubleshooting and other “what if” scenario exercises. Shorter development cycles for formula variations to target key paste attributes are one immediate benefit.

Copper plating is widely used in the electronic industry for fabrication of electronic devices. It is particularly useful for
fabrication of printed circuit boards and semiconductors. Copper is electroplated over the surface of a printed circuit board and onto the walls of the through holes. The mass PCB production requires intensification of and at the same time simplification of the metallization process without sacrificing but instead improving the reliability. Various approaches have been studied in order to plate high aspect ratio (AR) through holes with improved micro-distribution and improved mechanical properties of the plated copper such as Tensile Strength and Elongation. Direct current acid copper PTH (plating through holes) at low current densities as well as PPR plating for high AR (>12) were explored. The parameters of
a new high throw acid copper plating process are described in this paper. The mechanical properties and the thermal characteristics of the plated copper are presented. The results from the throwing power measurements are provided.
A high temperature acid copper process has been also studied. For a large number of PCB fabrication facilities in areas with hotter climates,plating at elevated temperature presents difficulties. Reduced brightness,increased grain size,and increased roughness lead to a decrease in reliability performance. A new process for plating smooth,bright,and planar copper layers at temperatures up to 40C is described. Tensile strength and elongation measurements as well as the thermal characteristics of copper layers deposited at room temperature and at elevated temperatures are given.