Paste release characteristics are driven by the Area Ratio formula,which is based upon conventional stencil foil materials such as a variety of stainless steel alloys,nickel,etc. The surface energy or “phobic” characteristics of these materials are significantly greater than the newer chemistries used to coat stencils and therefore effectively limits the conventional Area Ratio formula in its ability to predict transfer efficiency in ultra-fine pitch devices.

The next generation miniaturised SMT devices waiting to make their mark will require the assembly community to re think their processes and toolsets. The feature sizes that are involved in this new wave of miniaturisation are sub 200 micron,to put this into context,only a decade ago this would have been considered as Semicon domain.
Of all the process involved within the Surface Mount Assembly process the printer is certainly the most sensitive to these changes. But it’s not only about printing miniaturised features – the process engineer has to balance miniaturisation with the requirements of “standard” technology,thus we are experiencing the age of heterogeneous assembly.
Therefore the miniaturisation program is causing the print process to be challenged in new ways especially the impact on the available process window available to achieve high yield heterogeneous assembly
This paper will investigate the impact of miniaturisation and heterogeneous assembly on the print process and strategies to keep one generation ahead.In latest research work,actual paste deposit volumes and transfer efficiency have been monitored and compared for both square and round apertures with area ratio’s ranging from 0.20 thru to 1.35. This covers apertures sizes of between 100 and 550 microns in a nominal 100 micron thick stencil foil. In addition,the effect of ultrasonically activated squeegees (ProActiv) has been assessed as part of the same experiment. A further comparison has also been made between type 4 and type 4.5 solder paste aswell.
The data presented here will help provide guidelines for stencil aperture designs and strategies for ultra-fine pitch components such as 0.3CSP’s.

The structures of electronic components become smaller and smaller. 5 volts or smaller voltage of an electrostatic charge are enough to damage or change the structures in small electronic components. The structures will achieve such small dimensions,so electrostatic charges can cause permanent damages. In the year 2024 the sizes of the electronic components will be less than 10 nm. Electrostatic charges of 0,1 nC and electrostatic fields of 10 V/cm or 1000 V/m will be enough then to damage ESDS permanently. Many companies underestimate this danger.

Copper filling of laser drilled blind micro vias (BMV´s) is now the standard production method for high density interconnects. Copper filled BMV´s are used as solder bump sites for IC packaging where the filling process enables the required interconnect density and provides the surface to ensure reliable solder attachment. For “smart phone” production use of multiple lamination and typically 10 layers of stacked copper BMV filling is now the preferred technology,this is also known as the “any layer” filling process.
Advances in filling processes are required to maintain the development in circuit miniaturization together with the reduction in overall processing costs and to meet the demand for ever more filled BMV´s on each plated layer. The required filling processes must provide void or inclusion free filling,a minimum of surface plated copper along with the capability to allow stacked filled structures.
This paper describes the function and principles behind BMV filling processes together with methods for non destructive testing of the filled structures. Production processes for BMV filling in vertical and horizontal production equipment with both soluble and insoluble anodes are presented together with a discussion of the plating parameters currently used in volume production. A comparison in filling performance of DC plating with that achieved in reverse pulse plating is also made.
The impact of specific processing parameters on volume production systems is discussed and in particular the use of fully automatic process control and the advantages of such systems in achieving uniform and reliable product quality.

Electroless plating processes are popular because of their performance,reliability and cost effectiveness. The process combines unique deposit properties such as uniform plating build up regardless of geometry,excellent corrosion resistance,superior hardness and wear and the ability to plate on non-conducting materials. The most commonly used electroless plating process is Electroless Nickel (EN) plating using nickel phosphorus baths. The phosphorus content plays a fundamental role in all physical properties of the deposit. It is,therefore,critical to control the phosphorus content within a relatively tight range. X-ray fluorescence is an excellent method to not only measure plating thickness but also weight percent elemental composition of coatings. Previously,it was only possible to measure plated phosphorus content on steel substrates. New developments in XRF instrument hardware and software have extended the measurement application of electroless plating processes to nearly any substrate. The simultaneous measurement of thickness and composition is critical.

1.Conventional Flex
2.Basic Materials
3.Failure Modes
4.HDI Flex

Summary,conventional builds
Cautions in Design
•Average or above Design Expertise Required
–PTH to close to edge of part
–Panelization hugely impacts cost reduction
–Flex adhesive within PTH over 6 layers is a reliability concern
–PTH create sequential lamination
–Rigid-Flex arm length .25 inch MIN (2x .08) on conventional flex
–Keep simple flex simple
–RFQ early and often

The oven recipe,which consists of the reflow oven zone temperature settings and the speed of the conveyor,will determine a specific time-temperature profile for a given PCB assembly. In order to achieve a good quality PCB assembly,the time-temperature profile should be within the product and process specifications. This is determined by the solder paste,components and substrate tolerances. As a result,the accuracy of the profile becomes a critical element in the quality of the electronics assembly. The methods by which thermocouples (TCs) are attached to the PCB assembly,to record the profile as the PCB travels through the oven,significantly impact the measuring accuracy of the profile.
Many electronics assemblers do not have the luxury of sacrificing production PCBs and BGAs for the purpose of measuring their profiles. Yet they need to make sure that these assemblies are processed in spec.
Area-array packages have solder balls hidden under the package,making it particularly difficult to achieve the correct thermal profile. Improper melting of solder balls will lead to poor solder joint formation and will damage the BGAs or the entire assembly. These components also tend to be expensive and,hence,represent a particular challenge for assemblers.
The goal of this study was to identify a non-destructive method for TC attachment that provides a small offset to the “actual temperature under a BGA.”

For centuries,the squeegee blade has been used throughout many applications for depositing viscous materials through screens and stencils to transfer images on to substrates,from cloth material to electronic circuit boards. One area of blade printing mechanics that have been reviewed many times is the angle of attack of the blade. Typically it has been tested from 45 degrees to 60 degrees to optimize the printing quality and efficiency. However,this typically ends up as a compromise,from fill characteristics (45 degrees) to print definition (60 degrees). This paper will present the revolutionary performance of the profiled squeegee blade,which has recently been developed to create a virtual multi angle of attack for unsurpassed process control for all types of stencil printing processes.

The Two print stencils process has been a very useful tool in SMT Assembly and Package Assembly. It is also useful in Assemblies that require mixed technologies; including SMT / Through Hole,SMT / Glue attach components,Packages requiring die attach / SMT assembly. The concept is to print with a first print stencil which is thinner than the second print stencil. The second print stencil has relief pockets formed anywhere that the first stencil printed. It is useful for several applications:
Printing Solder Paste for Through-Hole and SMT
Printing Glue and Solder Paste
Printing Flux and Solder Paste
Printing Solder Paste for SMT and RF Shields
Printing Reservoir Solder Paste for multi-level boards
Printing Solder Paste and Reservoir Flux
Each of these applications will be discussed in this presentation.

The Printed Circuit Board (PCB) builds get ever more complex. With this the layer counts climb but the overall thickness remains the same. From this the cores of the build are reduced and the dielectric layers are reduced. When this happens there are more concerns regarding how these stack-ups can withstand higher voltage with the thinner cores. OEMs are making stronger requirements regarding dielectric withstanding. This paper will outline how the Electrical Test industry combats these requirements and provides solutions to adhere to these ever changing requirements. IPC states methods,ie TM-650 and IPC-6012 but these are guidelines. This paper will elaborate around these requirements regarding Condition A and Condition B from the TM-650 specification. The paper will also outline the opportunities around testing Dielectric Breakdown or HiPot. The paper will outline: HiPot Manual Testing HiPot Fixture Assisted Testing HiPot Full Automation Testing Voltages,dwell,ramp and current cutoffs will be explored. The paper will further extrapolate to educate OEMs the full guidelines regarding what HiPot testing is designed for and the difference for high potential individual net testing.
Reference Specifications: IPC-6012
IPC-TM-650
IPC-9252A