Two major trends in printed wiring boards electronics are applications that require higher operating frequency,often in the radio frequency range (GHz),and the use of lead free solder assembly. Material requirements for dielectric materials have become more stringent. Key characteristics for dielectric materials are low dielectric constant,low dielectric loss,high use temperature,and low moisture uptake. The use of engineering thermoplastics has been investigated as a means to enhance performance of thermoset resins. In particular,polyphenylene ether (PPE) exhibits excellent hydrolytic stability,low moisture absorption,extremely high glass transition temperature,outstanding electrical properties over a wide temperature and frequency range,and ease of flame retarding without the use of halogenated materials. Investigations on the use of engineering thermoplastics in thermoset resins have pointed out the complexities of the network molecular architecture. Indeed,a wide variety of network morphologies were obtained within the fully cured material. PPE telechelic macromers have been reported as a breakthrough in the search for materials that broadly enhanced performance of dielectric materials. Thus the use of PPE macromonomers as a co-reactant in epoxy resins resulted in extensive performance advantages. Indeed,the use of PPE macromoners in epoxy resins resulted in single-phase networks,exhibited an increase in glass transition temperatures (Tg),lower dielectric properties,lower moisture absorption,and increased toughness. Single-phase matrices were also obtained with cyanate esters that exhibited lower moisture absorption and increased toughness. Vinyl modified PPE macromers were used in resins cured via radical polymerization. These resins exhibited very low moisture absorption in addition to high Tg and very low dielectric properties. The advantages of PPE macromoners in enhancing key properties of various dielectric materials suggest utility in a variety of demanding electronic packaging applications.

The use of flexible circuit boards in the design and manufacture of electronic products has experienced a consistent and rapid growth over the last 15 years because their light weight and physical flexibility make it possible to combine electronics,packaging design,and styling to create exciting new consumer products. And as the capacity and pin density of electronic components has continued to increase,new demands are being created for flexible circuit boards. These new demands include the need for thinner copper on thinner flexible substrates with greater bending flexibility and durability.
The most common commercialized process today for the deposition of ultra-thin copper on flexible base materials is a vacuum sputtering process. In this process,there is a sputtered tie coat of chromium or other metals or alloys to improve the adhesion to the base,followed by sputtering of a thin layer,usually about 0.2 micron,of copper. Quite often the substrate is pre-treated with plasma to improve tie coat adhesion to the base material. This is often followed by the electro-deposition of copper to the desired final copper thickness. These products have been successful in the adhesiveless-copper-on-flexible substrate marketplace. However,the process is expensive because of the need for high capital cost vacuum deposition equipment,is energy intensive,requires the use of toxic metals,requires many processing steps,and is inherently single sided. In addition,the process requires additional processing steps beyond normal etching processes for the removal of the tie coat.
We are commercializing an innovative approach for metalizing flexible substrates. This new approach,which was developed
in the labs of SRI International (formerly Stanford Research Institute) is a non-vacuum process that eliminates the need for
expensive vacuum deposition,eliminates plasma treatment of base material,eliminates several expensive process steps normally associated with conventional copper coating techniques,and produces superior adhesion without the need for a tie coat. All of the process steps can be single or double sided,and have been implemented with a roll-to-roll manufacturing process. Flexible circuit materials made with this process can be used in most types of flexible circuit board manufacturing processes including subtractive and semi-additive methods. The copper deposited is ductile,and has good thickness tolerance. We have achieved outstanding adhesion to the base material along with good surface insulation resistance (SIR) and other pertinent properties. The process that has been implemented can produce coated copper with a thickness ranging from 0.1 micron to 18.0 micron. A variety of base materials have been studied with good results. These include polyimide,particle filled polyimide,liquid crystal polymers (LCP),polyesters,and composites. And the total process is inherently “greener” than existing materials and methods because of the elimination of most (99.95%) or all of the etched materials used in conventional subtractive and semi-additive processes today.

Embedded passives technology offers high-density high-performance solutions,but needs characterization before becoming a resource in harsh-environment applications. This paper discusses two critical factors: a) uniformity as-received from the fabricator,and b) long-term stability under extreme environmental conditions. PWB test specimens spanned a range of embedded resistors and embedded (distributed and discrete) capacitors,from several suppliers,using a variety of materials and processes.
Data as-received includes: Comparisons between target vs. measured values; board–to-board uniformity,uniformity of various spots on the same PWB; comparison edge-to-edge of the same board; and comparisons between coupon vs. PWB,Environmental stability data includes: values as a function of temperature; after long-term storage at elevated humidity and temperature; after vibration,long-term thermal-cycling,water immersion,
molten-solder-dip thermal-shock; and stability after surface over-heating.
As-received uniformity data reveals differences up to 20-40%) between the target value and the actual value,as well as among nominally equivalent features,and between coupon and board. Differences depend on type of element. This is before any cherry-picking or screening by the supplier. Tight fab process control will be necessary. Environmental stability is reassuringly robust. Most exposures cause relatively little change. Stability depends on materials,processes and geometries.
This information could help enable tolerances and yield expectations; develop QC sampling and acceptances protocols; and help designers’ qualification and performance expectations,under adverse in-service conditions.

Nickel plating is often used on PWBs to increase wear resistance and to prevent diffusion between copper and other plated metals. The nickel plating is often present in through holes as well as on the surface,such as when the entire PWB panel is nickel/gold plated or when press fit pins are used for assembly. When the plated through holes are evaluated by micro sectioning,it often becomes apparent that the nickel plating is not uniform. It tends to be much thinner in the middle of the hole than on the surface of the board,and may not meet minimum thickness requirements. This paper will evaluate the effect of various plating parameters and chemical additives on through hole plating uniformity. Data will be presented comparing direct current and pulse plating. This paper will also evaluate how the addition of chemical additives to increase throwing power affects the intrinsic stress and grain structure of the nickel. Tests include plating PWBs having through holes of varying diameters and aspect ratios with nickel in thicknesses up to 100 mils. Nickel thickness and uniformity are evaluated both by microsection and X-ray fluorescence measurement techniques.

Phenolic cure of epoxy resins produces high glass transition temperature materials for electrical laminates fabrication. These resins are brittle due to the high crosslink densities. Consequently,this causes high drill bit wear and breakages along with poor drill-hole quality during board fabrication. This can increase cost and pose a reliability concern for the printed circuit board (PCB) industry. A smooth drill-hole wall surface facilitates even copper plating and reduces locations where small cracks or defects can be initiated that can lead to conductive anodic filaments. The current challenge is to incorporate toughening technology that will enable a high Tg,highly cross linked epoxy resin to pass performance tests,reduce drilling costs,and provide smooth hole walls for improved reliability. Furthermore,development of a correlation between PCB drillability and material properties of the composite laminate is critical.
In this work,the drill-hole surface roughness for epoxy formulations toughened with different tougheners is presented. Results show that the drill-hole surface of a non-toughened system suffers brittle failure particularly in the resin-fiber interface. A toughened system,on the other hand,exhibits a smoother drill-hole surface that resists failure in the fiber-resin interface.

In order to meet the never ending desire for smaller and cheaper electronics,many companies are pursuing the use of embedded passive technologies. There are several examples of embedded
capacitors,especially for digital functions such as decoupling. Up to this point however,it has been more difficult to use embedded capacitors as part of RF circuitry such as filters. This is due to the
fact that most materials used for forming embedded discrete capacitors have relatively high loss at GHz frequencies. Also,the capacitance density can change as a function of frequency and
temperature and affect the performance.
New materials have been developed to address the loss and capacitance variation of the typical embedded capacitor materials. The paper will show a comparison of the new versus existing
materials used for embedded capacitors and demonstrate a lower temperature coefficient of capacitance (TCC),lower loss at frequencies up to 10 GHz and stable capacitance density to 10 GHz.
In addition,several manufacturing techniques will be shown to incorporate this material into an organic chip package,as well as ways to minimize the variation of the electrode areas to improve
total tolerance.
In summary this paper will show a path for those who are designing RF modules on LTCC (due to stable performance) a way to reduce cost by going to organic packages and incorporating embedded capacitor materials.

The fabrication of EPAD PWBs have come about in response to the pursuit of reduction in real estate,demand for improved electrical characteristics and higher durability and reliability needs from the end user. The circuit board uses of ALIVH (Any Layer Interstitial via Hole) technology and thinner components have made the manufacture of EPAD PWBs possible.
The major concerns of fabrication are the thinness of the substrate,thinness of the components and the narrow pitch of the ICs. The substrate thinness will lead to deformation of the PWB. During the SMT process,components can be chipped or cracked due to their thinness and substrate thermal expansion characteristics. The narrow pitch of the ICs (C4-FC) can lead to opens due to the same characteristics of the substrate mentioned earlier.
The Flake on Film process combines several tools and processes to deliver a complete package in the manufacture of EPAD PWBs. The use of a Joint Protection Solder paste adds a bonding agent that coats the surface of the solder to the substrate to minimize cracking during and after reflow. The PWB is mounted to an adhesive backed carrier with suction holes for vacuum support and used for the entire SMT process from printing to reflow. After reflow the carrier is separated from the PWB and reused. The use of a Stamping Unit increases the solder volume on the balls to insure proper wetting and the use of the APC system places the components centered to the print to insure proper contact. The use of the FoF process will increase the overall productivity by controlling all aspects of the SMT line from solder paste to reflow.

As some of the reliability issues and cost associated with tin silver copper solders become more apparent,alternative pb-free solder formulations are being considered. Of particular interest are those that feature little or no silver. However,the thermo-mechanical reliability of these solders is not well known because the main focus has been on improving the mechanical shock/drop performance of the solder interconnects. This study presents preliminary thermal cycling data for a tin nickel copper soldered area array chip scale package. This data is then used to develop a 1st order analytical model to make thermal mechanical fatigue life predictions. The model uses basic distance to neutral point and continuous attach type equations to predict the strain energy dissipated by the solder joint. The energy dissipation is used to make fatigue predictions.

The low Ag solder alloy shows higher drop performance than the high Ag solder alloy in the every kind of package and board combinations. This is related to the ductility of solder and the surface between solder and pad.
The unstable interface exists in IMC,pad material,and solder bulk,aroused by the lattice mismatch,which enables the thermal and physical stress due to the continuous exterior shock to transfer to the IMC interface. Therefore,it must be strongly requested to control solder morphology,and also shape and thickness of IMC for improving the solder reliability.
Furthermore,the solder alloy with high Cu shows good drop performance. We can analogize from this Cu performance that high Cu plays an important role in relieving the brittle surface,such as Ni-P layer,being appeared on electro-less pad after reflow.

Solder joints tend to crack after extended thermal cycling,if the component and the circuit board are CTE mis-matched. Predicting this t-cycle lifetime is critical in optimizing product design or in-service conditions. Predictor models embody cyclic fatigue physics and math,and require inputs of the materials and geometry of the hardware,as well as the thermal conditions of the environment. The output is the predicted number of t-cycles to fail (i.e. to develop electrical-open cracks thru the solder-joint). Several predictor models are in use within the industry. All have strengths and weaknesses,and offer different results. This paper compares several models,rating them for ease of use,and for accuracy against actual test results and against each other. The study uses a round-robin approach; wherein each participant was given the same input data for ten different components,but the actual were withheld until the respective predictor results were in. Also,this paper describes a related study on the ability of each model to perform parametric analyses: i.e. to define the effect on t-cycle life of variations in hardware and environmental conditions. The results offer guidance on selecting models for t-cycle life prediction,as well as on understanding options for improving t-cycle life.