Embedded components technology has launched its implementation in volume products demanding for highest miniaturization level. Small modules with embedded dies and passive components on the top side are mounted in hand held devices. Smart phones are the enablers for this new technology using the capabilities of embedded components. These modules have already shown a high level of reliability which has been a pre-requisite to get acceptance for volume products. Embedded dies are relative small with dimensions of about two by two millimeter and therefore all critical topics like the CTE mismatch of components and PCB materials,process die attachment are on a non-critical level. The roadmaps for the application development show a drastic increase of the complexity of the modules and in parallel increasing I/O numbers and die dimensions. Applications in the development pipeline show already die dimensions of seven by seven millimeter.
Based on this development roadmap a simulation project was started with the Material Center Leoben and Thales Global Services to evaluate the stress situation of embedded components and to build a thermo mechanical simulation model. The verification of this model was started by characterization of silicon dies and embedding of standardized components into PCB to get detailed stress parameters for these components. The next step of simulation deals with the simulation of embedding processes. Die assembly is the first process followed by the lamination process to form the embedded core. For the assembly process a DOE has been done to correlate the results with the simulation model.
All along the European funded FP7 HERMES*project huge efforts have been deployed in order to characterize the reliability of active and passive embedded chips,as well as packages assembled on the outer layers of the PCB . To achieve a high level of reliability of future complex modules using HERMES technology,work has been done to address different aspects like process optimization including different build-ups,best choice of base material,different size of active dice and design rules,knowledge of failure mode.
HERMES was successful closed in February 2012 and the final results of the HERMES embedding technology are shown in this paper. A dedicated test vehicle using a 4 (level of stacked µvia) +core +4 simulating a functional demonstrator have been manufactured and stressed under accelerated thermal cycling in the range -40°C/+125°C and under continuous monitoring.
This test vehicle includes embedded chips of different sizes,passive chips and BGA/QFN package assemblies on the external faces of the PCB. The design permits to isolate component (in daisy chain) and interconnections to facilitate the reliability and failure analysis. A detailed construction analysis of the manufactured boards has been done before to start the reliability test in order to have a reference.

An electroless nickel (EN) layer is frequently used in various industrial applications. Commonly it is used as the barrier layer in electroless nickel/immersion gold (ENIG) as a solderability preservative for the electronics industry. The finish provides excellent corrosion resistance and good solderability. A shortcoming of this process is the potential for a hyperactive corrosion of the nickel surface during immersion gold plating. The resultant defect displays itself as a gray or black appearance at the nickel/gold interface,known as “Black Pad” or “Black Line Nickel”. It is important to determine and control the corrosion properties of an EN deposit during an ENIG process to obtain high quality products. Unfortunately,quantitative analysis of corrosion resistance of the EN layer has not been established in the field of PCB. In this paper,an electrochemical method via sequential electrochemical reduction analysis (SERA) instrument to quantify the corrosion resistance of the EN deposit is proposed. The data obtained via the electrochemical method was analyzed and correlated to the deposit properties of the EN. The method is easy to use and can be applied for quantitative analysis in industrial EN processes.

An accelerated thermal cycle experiment comparing similarly constructed area array devices representing Land Grid Array
(LGA) and Ball Grid Array (BGA) technology with 0.254,0.30,and 0.40mm diameter SAC305 solder balls was performed. The devices were subjected to three thermal cycle conditions in order to promote 2nd level solder fatigue. Failure data was compared using Weibull analyses. The results show that time to failure is highly influenced by the package pitch and thermal cycle temperatures in a manner predicted by simple mechanics. However,there were instances in which the effect of solder ball size did not fit the traditional solder joint reliability model in which increasing solder joint standoff height improves reliability (i.e. more cycles to failure). A theory is proposed that substantial differences in SAC305 solder joint Sn grain morphology may explain,at least partially,the discrepancies and evidence to support this theory is presented.

Based on the trend for new technology in the automotive market including high power modules for e-mobility,and a combination of logic and power which will be developed for the future market with economic,safety and reliability effects. One of the most important challenges are electrical systems and the realization of complete energy management. The connection between sensor,logic and control units,as well as power transmission for electrical vehicles,is the assembling technology for electronics (eAVT). This paper will discuss and show results of reliability with soft soldering alloys (based on lead free) for higher temperature (>125°C - 175°C) as well as possibilities for different applications. Therefore,it will present the basis of the material and the realization for processes for the e.AVT. Furthermore alternatives and development stages for temperature more than 200°C will be discussed.

Lead Free Technology has brought new materials and different quality concerns to the Electronics Industry. For that,the creation of new methods to determine the quality of materials is needed and preferred. Intermetallic compounds for example can grow faster in lead-free metallization and decrease the possibility to form good joints. For that,a new method to measure IMC layer thickness is presented. This new method uses a combination of X-Ray Fluorescence Method (XRFM) and Coulometric Stripping Method (CSM). XRFM is capable to measure percentage of elements and correlate the values to their layer thickness. This procedure makes XRFM not so suitable to measure intermetallic thickness when it is growing because the elements only combine each other and are not removed; therefore XRFM gives similar values in thin metallization layers of tin-copper with thick or thin IMC layer,for example. On the other hand,CSM removes pure element layer using an electrochemical depletion. The combination of both methods allows evaluating the IMC layer thickness in a more precise form. For validation of the method,SEM/EDX and Auger microanalyses were made to compare values. Besides,several experiments were carried over in several temperatures and reflow profiles to measure IMC growth in Chemical Tin PCB’s. The results were used to develop a more precise equation to predict the IMC growing. The new equation uses the Activation Energy depending on the IMC thickness.

•Transition to Pb-free soldering is incomplete for high reliability or high temperature applications
•For those not fully converted into Pb-free,mixed system is common due to lack of some Pb-containing components
•Mixed system encountered voiding problem,particularly for BGA applications
•Miniaturization aggravate vulnerability of device toward voiding
•Unravel voiding mechanism of mixed system critical for DFR for solder joints

Conclusions:
•Tin/Lead BGAs: The location of the void within the solder joint was the primary root cause for the loss of solder joint integrity.
•Lead-free BGAs: The statistical analysis and the metallographic cross-sectional analysis results revealed that the presence or size of the solder joint voids did not correlate to the loss of lead-free solder joint integrity.
•A single set of BGA solder joint void process control limits is applicable for both tin/lead and lead-free BGA solder joints

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- Nanosolder on multi-segment nanowires have been successfully fabricated by electrodeposition method;
- Flux assisted environment enhanced reflow result and micron scale solder spheroids formed on non-wetting Si substrate;
- Nanosolder reflow performance on reactive Cu substrate was studied;
- 1-D interdiffusion on Cu-Sn two-segment nanowire were observed through the thermal heating and e-beam irradiation;
- Nanojoints formed between nanowires and a network was constructed through quasi-reflow process in liquid.

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