Conductive Anodic Filament(CAF) that is one of the copper migration phenomena becomes significant problem with higher density circuit for printed circuit board.(PCB) In the past CAF property was judged the test vehicle included through hall(TH) (wall to wall 0.3-0.5mm) Recently the circuit of PCB becomes higher density,the evaluation vehicle is requested more narrow TH pitch. So we had studied drilling process ability and the structure of PCB,finally we made evaluation vehicle that can evaluate anti-CAF property by using very narrow pitch TH(wall to wall 0.05-0.10mm) We tested several laminates to use this test vehicle and found out one of high Tg halogen-free FR-4 had an excellent anti-CAF restraining property. Additional our migration test to use extract liquids indicated the different trend between good CAF property’s laminate and bad one.

The purpose of this paper is to demonstrate the value of mathematical modeling of PCB processes. This approach will identify the first order variables that control the process and the relative influence of each of these variables upon the performance of the process. The time constants associated with the variables which define when process equilibrium is achieved are also identified. This information can obviously be used in setting the process. In addition,it will eliminate the need for guess work that normally precedes a DOE in establishing the variables controlling the process. All too often in organizing a DOE first order variables are overlook or minor variables included. Consequently,the results are either meaningless or the time required to carryout the DOE is excessive.
For purposes of this discussion the focus is on an inline,counter flowing processor. These machines are used for a variety of tasks including resist removal,etching and cleaning. In most cases,the machines are multi chambered,with a counter flowing chemical solution. The solution is normally pumped from the chamber to spray nozzles which deliver the solution to the work piece; a PCB panel. After impinging upon the panel the solution drains back into the chamber along with the dissolved superfluous material.

Following the implementation of WEEE legislation,there will be an increasing interest in adopting more sustainable manufacturing processes and materials as targets are increased,and must be achieved without a loss in performance. These innovations may well lead to alternative failure modes. This work studies the performance of specific favoured materials to qualify the failure mechanisms and the effective stress screening regimes,and hence put in place the underpinning work for developing a test method for characterising these materials.
Three systems are evaluated; thermoplastic printed circuit assemblies based on copper-clad polyetherimide,polymer thick film on PET,and direct write copper on PET,were assembled using electrically conductive adhesives and tested using damp heat,dry heat and thermal cycling. All combinations showed very good reliability during the arduous testing. Chip resistor components generally showed less than 5% failures due to increased joint resistance after 1000 hours at 85°C/85%RH or 1000 thermal cycles from –55°C to +125°C. Results from gull-wing SOIC components were less promising but current work is investigating assembly methods to improve reliability of these components. Results were found to be conductive adhesive dependent,but results show that if the right combination of materials is chosen,thermoplastic substrates can be reliable for a wide range of electronics applications. The thermoplastic substrate technology offers great flexibility,for example 3D manufacturing or using the housing as the circuit board are all feasible. The lower energy and cost of manufacture and the improved potential for recycling indicate the value of further work.

REACH presents a new set of direct and indirect risks for article manufacturers,including electronics manufacturers. Direct risks arise from obligations explicitly outlined in the REACH regulation itself – article 7 and article 13. Indirect risks arise from upstream and downstream supply chain ripple effects caused by REACH. These ripple effects will impact article manufacturers,including those who do not import directly into the European Union. Article manufacturers – particularly those with complex products and supply chains – are adopting data-driven risk management approaches to help ensure the future viability and profitability of their products. This presentation presents a framework for electronics manufacturers to identify and mitigate their REACH risks,both direct and indirect. A fact based and systematic approach is outlined,describing what product and supply chain data are needed and how to make decisions based on this data. This paper is based in part on the REACH initiatives underway at several large multinational manufacturers.

Although the official implementation of the EU Restriction of Hazardous Substances (RoHS) directive officially started on July 1,2006,a significant portion of the avionics electronics supply chain began a wide variety of transition actions in the years prior to the implementation deadline in an effort to understand material issues and fabrication concerns. Original Electronic Manufacturers (OEMs) of avionics equipment were either exempt (military products) or excluded (commercial products) from the EU RoHS requirements due to the legislative directive being a single market initiative. However,due to the fact that components used in the avionics industry are largely common with those used in the affected consumer markets,Rockwell Collins had no choice but to begin proactively addressing these issues/concerns back in 2003. The objective of the investigation was to conduct a feasibility study using a functional avionics design to determine printed wiring board design and potential printed wiring assembly issues/concerns when using Pbfree soldering processes/procedures for military avionics products. Environmental Stress Screen (ESS) testing was completed demonstrating that the lead-free military avionics unit was equal to the typical tin/lead military avionics unit test results for the conditions used. This information will be incorporated into the Rockwell Collins Lead-free Control Plan (LFCP) knowledge database as customer information.

Since July 1st 2006,the 2002/95/EC RoHS European directive has forced the electronic industry to switch from Tin-Lead to lead-free soldering alloys for components assembly.
Exemption domains have been defined for highly failure sensitive applications with long service lifetimes like military and aerospace because of the lack of knowledge on long term solder joint reliability in harsh environment. Furthermore,the physical properties of lead-free solder alloys (such as SAC) greatly differ
from those of well known Tin-Lead so that well established accelerated tests can’t be replicated for lead-free to forecast lifetime. These tests are not yet defined and moreover,the statistics of failure mechanisms and rates from the field are not sufficient to manage the reliability risk for many kinds of THALES products.
However,component manufacturers have changed their package finish to comply with the RoHS directive without taking into account AHP equipment makers due to their low share in volume. As a consequence,AHP companies have to face this difficult situation: either manage the obsolescence by component storage
with the great difficulty to forecast the customer demands,or find a solution to use lead free package finishes with standard Tin-Lead alloy,particularly sensitive with all kinds of BGA.
Thales shared a cooperative and ambitious technological program with CELESTICA as a key partner in order to secure an industrial process solution called hereafter SnPb+ (mixed metal assembly).
This paper describes microstructures and thermal cycling performance of lead-free ball grid array and leaded components assembled with Sn-Pb solder using conventional SnPb reflow and reflow with temperature higher than 217°C to melt the lead-free ball and insure a full mixing (the SnPb+ process). The formation of
uniform and non-uniform microstructures as a result of Sn-Ag-Cu (SAC) solder ball dissolution in a molten Sn-Pb solder using a conventional SnPb reflow or melting is studied. The difference in mechanisms and performance of uniform fully mixed and non-uniform partially mixed joints as a response on thermal cycling
at -55°C to 125°C conditions is explored. Additional attention is paid to Sn-Bi finished QFPs and TSOPs. It is shown that Sn-Bi finish with 3 -5% Bi is not responsible for early failures if it is used with Sn-Pb solder.

Over these years,EU RoHS restriction and lead-free capability is the hottest environmental protection subject. In technology trend,signal integrity performance gets more critical upon today’s higher signal transmission speed demand in every field of applications such as computer CPU and GPU chipset levels,system operation frequency and a variety of communication bus and cable like PCI express,SATA II and AGP bus for computer system. Signal communication speed will shift from 1-5 Gbps range up to 5-10Gbps depending on applications. In order to meet lead-free ingredients and severe processes conditions with capable signal integrity performance,laminate material will play a more and more critical and sensitive role in the system.
From consumer products to high-end applications,they all need certain electrical and thermal performances; it is therefore essential to meet those requirements with cost effectiveness. As a base material supplier,we will hereby discuss material design and factors that influence signal integrity,including epoxy and hardener,resin chemical construction,laminate ply-up construction,amount of resin content,fabric weaving density,moisture pick-up and environment factors etc. for a massive mainstream application and low loss application under the hypothesis of lead-free capability.

We demonstrate here a novel CCL (Copper Clad Laminate) which exhibits an extremely low transmission loss at mm-wave band. The CCL which we developed is based on a new fluoropolymer with adhesive characteristics. In contrast to conventional PTFE,the adhesive fluoropolymer allows us to apply a wholly dry process for CCL fabrication,which contributes to environmental load reduction.
It is well known that the factor of transmission loss mainly consists of conductive loss and dielectric loss. However,in conventional CCL data sheets,only the loss tangent data at specific frequencies are disclosed. Neither the dielectric loss nor the whole transmission loss at the other frequencies is known. In order to minimize the transmission loss at mm-wave band,the quantitative analysis for those factors is essential.
We proposed the evaluation method which can clarify not only the dielectric loss but also the conductive loss of CCL up to 110GHz. Several transmission lines with different impedance were measured and analyzed; the two different losses were discriminated in straight forward manner. Besides the evaluation method,a highly accurate measurement technique for low loss transmission line was achieved.
Using several kinds of surface roughness of copper foil,we made CCL test samples and evaluated the transmission loss by the above-mentioned method. Since the results indicated that the surface roughness of copper foil remarkably influenced the transmission loss,profile free copper foil was used for developed CCL. Due to the adhesive characteristics of new fluoropolymer,enough peeling strength was obtained without extra surface treatment.
Finally we benchmarked our developed CCL to the Rogers RT/duroid 5880,world lowest loss characteristics,and the result showed improved loss characteristics compared to RT/duroid 5880.

The peel test will be reviewed,with special attention given to deposited adhesiveless copperclad laminates. A basic familiarity with the IPC test method will be assumed. The brief amount of time allotted permits focus on two general topics.
First,data will be presented to illustrate the influence of a number of variables on peel strength values,such as conductor thickness,conductor width,and copper treatment,as well as more subtle things such as surface finish and even simple choice of test method.
Second,a detailed comparison of adhesion performance between deposited materials and their cast and laminated cousins will be provided as well.

The Semiconductor industry is demanding more and more from today’s PWB manufacturers. This paper offers some insights to the needs,requirements,solutions and process verifications that R&D Circuits has spent years analyzing and perfecting for its customers in the industry.
The industry in question is known as the A.T.E. or Semiconductor test industry. The need is to electrically test or characterize a packaged device,prior to it being shipped to OEM’s for use in their electronic devices. The package size continues to decrease,while the test regimen gets tougher and tougher. The fine pitch of devices is pushing PWB manufacturing to the far limits of capability. Six mil diameter holes drilled and plated in 0.187 thick panels (30+:1 aspect ratios) is truly on the edge of that manufacturing capability.
New techniques in drilling holes,prepping them for the subsequent plating processes,of which DRPP has proven to be a crucial step for us,and finally solid verification of those steps is a fundamental requirement for any PWB manufacturer,looking to build PWB’s for this demanding industry.
Data is provided to validate the process techniques,utilizing the IST test methods,simply show that while the attributes are not those you would see in traditional PWB’s,reliable and repeatable A.T.E. boards can be produced.