Printed Electronics is considered by many international technologists to be a platform for manufacturing innovation. Its rich portfolio of advanced multi-functional nano-designed materials,scalable ambient processes,and high volume manufacturing technologies lends itself to offer an opportunity for sustained manufacturing innovation. The success of introducing a new manufacturing technology is strongly dependent on the ability to achieve high final product yields at current or reduced cost. In the past,standards have been the critical vehicles to enable manufacturing success.
During the past few years the Printed Electronics Field has seen an increase in the number of companies attempting to scale-up their manufacturing processes for new product introduction. A key operations-related activity during this exercise is the establishment of a robust supply chain. Many of the printed electronics companies have negotiated unique quality conformance documents (i.e.,Certificates of Compliance) with each individual supply chain member. Also,these companies have made significant investments to develop internal standard operating procedures.
Historically,the adoption of standards has shown that it facilitates the growth of an emerging field and reduces the burden placed on individual companies to invest significant resources in the development of company specific compliance documentation. This paper provides an overview of the recently established IPC Printed Electronics Standards initiative.

There are few halogen free flame retardant laminates available and for those on the market currently,they are not considered mid loss and thermally stable. Theta circuit materials appear to be unique where they meet both these criteria along with other necessary requirements for good PCB fabrication and reliability. The difficulty is comparing materials to this unique material fairly. The appropriate comparisons were done here with materials that have a long proven record in the PCB industry and as a group these comparison materials have the attributes to verify thermal stability and mid loss performance. Through multiple lead-free solder reflows,288°C solder floats,eyebrow crack testing and other demanding high reliability tests not addressed in this paper,such as HATS,CAF,IST,liquid-to-liquid and moisture conditioning,it was found that this newly developed halogen free material is very
thermally stable. The electrical properties were found to be very good as well. The claim of a mid-loss material was verified from insertion loss testing compared to well-known low loss and high loss materials. Also,material dispersion of the dielectric constant was found to be very good and consistent over frequency which can enable a much more stable eye diagram for high speed digital applications.

Consumption electronic devices are becoming much smaller,lighter and multifunctional,and high CTI application has
already been not satisfied with double sided design and requested thinner & multilayer compatible. We developed a new
halogen free and high CTI RCC to meet these new requirements. Compared to traditional FR-4,it provides flexible
selection by combination with different material to meet fine line,lead free & halogen free application.

Tetrabromobisphenol-A (TBBPA) is the predominant flame retardant used in rigid FR-4 printed wiring boards (PWB). In
this application,the TBBPA is fully reacted into the epoxy resins that form the base material of the PWB. TBBPA’s
leadership position in the rigid printed wiring board market is due to several factors,which include reliable performance over
time. This paper will look at the benefits of TBBPA as a flame retardant in epoxy resin PWBs. It will also address the
current regulatory status of TBBPA. An update will be given on the regulatory and environmental status of TBBPA and
other industry assessments that compare TBBPA to alternative flame retardants for PB will be included.

We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal
cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold
(ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less
than 10 ?m line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the
palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd,Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd,Ni)Sn4 or
creeping of (Pd,Ni)Sn4.

This paper will discuss a new approach to the final finishing for the PCB industry which is based on the use of an ultra-thin
fluoropolymer film as a protective coating to preserve solderability of the circuit board between manufacture and assembly.
The coating has been shown to extend the shelf life of the PCB by preventing oxidation and corrosion,and ensures excellent
solderability during assembly. The fluoropolymer coating is applied using a dry plasma deposition process,which eliminates
the use of harsh chemicals and waste streams associated with other surface finishes. The coating has been applied directly on
to copper,or can be used in conjunction with other surface finishes to act as a corrosion inhibitor when specific properties are
required,such as resistance to creep corrosion or tarnish.
Significant testing has been performed on the fluoropolymer coating to demonstrate its capability as a surface finish for the
PCB industry. The results of solderability testing,solder joint reliability testing and corrosion protection will be discussed.

As a surface finish,electroless nickel / electroless palladium / immersion gold (ENEPIG) has received increased attention
for both packaging/IC-substrate and PWB applications. With a lower gold thickness than conventional electroless nickel
/ immersion gold (ENIG) the ENEPIG finish offers the potential for higher reliability,better performance and reduced
cost.[1,2]
This paper shows the benefits by using a pure palladium Layer in the ENEPIG (Electroless Nickel,Electroless Palladium,
Immersion Gold) and ENEP (Electroless Nickel,Electroless Palladium) Surface Finishes in terms of physical properties
and in terms of gold wire bonding test results.

There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices,the emergence of lead-free processing,and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide.
Over the past decade,the shadow moiré technique has become the method of choice for temperature-dependent warpage measurement. It is estimated that there are over 200 such machines installed worldwide. However,as the above-mentioned industry trends began to emerge,certain limitations of shadow moiré became apparent,such as camera resolution restrictions,schematic limitations on heating/cooling mechanisms,and data processing techniques that can affect accuracy. As a result of recent developments in projection moiré technology,these issues have been addressed,and the technique is poised to meet the future requirements of the microelectronics industry.
In this paper we discuss projection moiré as a new technique for warpage measurement of advance packages,with applications in failure analysis,new product qualification and process control. Projection moiré addresses many shadow moiré limitations,including camera resolution,heating uniformity and noise.
Key words: warpage,failure analysis,interconnect defects,moiré,shadow moiré,projection moiré,coplanarity.

With the advent of larger packages and higher densities/pitch the Industry has been concerned with the co -planarity of both
the substrate package and the PCB motherboard. The iNEMI PCB Co-Planarity Working group generated a snapshot in time
of the dynamic co-planarity of several PCB’s designs from four market sectors. This paper presents the summarized results
of the project’s investigation of the question if room temperature co -planarity measurements can predict the co-planarity at
Lead-Free assembly temperatures. This paper will also investigate the trends in dynamic co-planarity between market sectors
and global versus local area of concern measurements as well as share the learning and issues of undertaking dynamic co -
planarity measurements of PCB motherboards.

Coreless technology in package substrate has been developed to satisfy the increasing demand of lighter,smaller and superior electrical performance regarding as the future trend in electronic application. However,there are major challenges of reducing coreless substrate warpage in terms of both substrate manufacturing and assembly process. Substrate manufactures typically provide substrate warpage within satisfying customer’s specification which does not allow much margin left in assembly considering the number of reflows and curing profiles which the package undergoes during assembly. However,it is very difficult to provide satisfying this level of warpage because coreless substrate is one-third as thin as conventional one and does not use stiff core material. The key element for success in coreless technology is to solve the warpage issue at manufacturing site because the decrease of bare substrate warpage is important to improve the assembly yield. To figure out these problems,design optimization,mechanical/thermal treatment and low CTE material are suggested in this study. Final part discusses assembly result and issue for future work.