Excessive moisture entrapped/absorbed within printed board laminates can expand during soldering operations,causing delamination or other damage. While moisture absorption data is available for some materials used in PB construction,little information has been made available for finished PBs,where not
only the laminate material is important in moisture gain or loss,but also the board thickness,copper content,details of the construction,and assembly process conditions. This study measures moisture absorption and desorption rates within various representative rigid multilayer PB structures,under varying conditions of temperature and humidity,including shop ambient environments and baking operations. Weight gain or loss attributable to moisture was measured using an analytical balance. The effectiveness and response times of humidity indicator cards used in PB packaging was also assessed. This information may be used to develop process controls for PB fabrication or PB assembly operations,dry storage practices,or baking procedures.

This presentation will review the findings of a HDPUG consortia effort to evaluate 29 different bare board material and stack-up combinations and their associated performance after 6X Pb-free reflows at 260C. Data presented will focus on the air-air thermal cycling results. IST testing and material survivability after Pb-free assembly reflow portions of this testing are also presented. Test board design aspects,manufacturing processes,Weibull analysis and failure analysis data will be presented. The impact of “plated through hole pitch” on laminate integrity and how material properties relate to the results will be discussed.
This presentation was originally presented by Joe Smetana (ALU) at the APEX 2009 conference,and it be presented here again at the request of the mid-west IPC committee.

Recent increases in assembly temperatures in response to removing lead from solder used in printed circuit boards (PCBs)
assembly has increase the strain and stress on interconnect structures. The elevated assembly temperature has reduced the
reliability of interconnect structures including microvias. This paper addresses how microvias may fail in response to the thermal excursion associated with assembly and the end use environment. The logic of different elevated temperature testing on FR4 (G10) and polyimide materials is reviewed. The paper compares and contrasts the implications of testing the microvia passively and under an electrical load. Also addressed are microsectioning techniques to improve the acuity of microscopic analysis. The failure modes addressed include separation between the base of the microvia and capture pad,microvia barrel cracks,and corner cracks,circumferential cracks around the base of the microvia in the capture pad and microvia misregistration to the base of the capture pad. This paper addresses the reliability implications of microvia constructions including stand alone,staggered,stacked microvias,copper and epoxy filled microvias and the failure modes
unique to these structures.

As more electronic assembly moves from OEM to EMS providers,a number of key issues arise in the overall value stream of production. This presentation will provide a comprehensive look at quality and reliability issues in circuit assembly processes from one of the world’s leading EMS providers. OEMs,material and component suppliers,and
EMS companies will gain valuable insight on how to avoid these pitfalls and directly impact their bottom line.

This presentation attempts to convince the reader that while all the logistical,equipment,financial and process aspects of any business are important,the high performance work team is the critical factor for success and defining difference,especially in the EMS (Electronic Manufacturing Services) industry.
It’s a relatively simple matter to replicate equipment and logistical strategies with enough money and time. Also,most of the day to day manufacturing processes are not terribly difficult and most are not proprietary. What is very difficult to achieve is a highly functioning team hitting on all cylinders with a minimum of wasted energy on organizational politics. Some “Lean Enterprise” concepts will be discussed as they apply to work teams.
The presentation will address tactics and strategies for developing,maintaining and continually improving the effectiveness of the EMS team.

Many will look to IPC standards for advice or workmanship requirements for electronic assemblies. Some will find a copy of IPC-A-610 Acceptability of Electronic Assemblies and stop there. But IPC has many other tools that can help improve quality and reliability for companies involved in manufacturing electronics. This presentation will tour the factory floor and point out some of the best and often overlooked resources from IPC.

Little data has been generated on the performance of lead-free solders under vibration and mechanical shock. What data exists suggests that lead-free solders may be less reliable than eutectic SnPb solder when used on area array components (e.g.,BGA's). This presentation is designed to educate the audience on how vibration and mechanical shock tests are typically conducted and on how to interpret test results. Test data from the literature and from several lead-free consortia will also be presented.

At present there are a large number of materials that have been proposed as replacements for lead containing solder for reflow and wave and selective soldering.
Unlike solder paste in a reflow process,solder in automated processes changes in composition and impurities with time as the solder is utilized. There currently are no contamination limits for lead-free solder in J-STD-001D. The contamination limits listed in J-STD-001D only apply to tin/lead solders.
Given the limited amount of data available at present,the IPC SPVC members have undertaken a study to determine the “Take Action Limits” (TAL) of solder pot contamination for SAC305 lead free solder. (As the number of lead free alloys currently in use for automated soldering processes is too large for a comprehensive study in any reasonable time frame,the IPC SPVC members,after deliberation,decided to limit the initial work to the SAC 305
(96.5%Sn,3.0% Ag,0.5% Cu) alloy.)

Although lead free assembly is now widely adopted the industry is still exploring a variety of options for lead free alloys. Attempts to standardize on a single alloy for either reflow or wave solder assembly have not been successful. Indeed,if anything,the proliferation of new lead free alloy types has increased.
For OEMs and EMS this poses a problem. All lead free alloys in general use,e.g. SAC 305,have a mix of desirable and not-so-desirable properties. It is the “not-so-desirable” properties,especially in contrast with the well known Tin-Lead systems,that make lead free assembly a process that poses unique
difficulties and has a small process window. Solder suppliers,responding to these assembly problems,have proposed a large number of new materials that specifically address many of the vexing manufacturing properties of the first lead free alloys on the market. However,many of the first alloys introduced,e.g. SAC 305,are,if not completely characterized,better understood in terms of reliability properties than the new alloys being introduced. So while it is tempting for assemblers to look to the new alloys as solutions to the manufacturing issues of the “older” materials the lack of reliability characterization of these new materials introduces an element of uncertainty when compared to the current lead free materials in general use.
To address this problem the IPC Solder Products Value Council (IPC SPVC) in cooperation with several leading OEMs and EMS providers is developing a set of test protocols for evaluation of new lead free
alloys on the basis of their physical properties,e.g. creep,and their performance in the assembly of a standardized test vehicle. This talk will focus on the physical testing aspect covering the genesis of this effort,input received from industry experts and the current status of the draft standard. The goal of this new test standard is to reduce the time and effort required to characterize an ally and thus help manufacturers improve their assembly processes without jeopardizing reliability.

Cracking and delamination defects in printed circuit boards (PCBs) during elevated thermal exposure have always been a concern for the electronics industry. However,with the increasing spread of Pb-free assembly into industries with lower volume and higher complexity,these events are occurring more frequently. Several telecom and enterprise original equipment manufacturers (OEMs) have reported that the robustness of their PCBs is their number one concern during the transition from SnPb to Pb-free. Cracking and delamination within PCBs can be cohesive or adhesive in nature and can occur within the weave,along the weave,or at the copper/epoxy interface. The role of moisture absorption and other
PCB material properties on this phenomenon is still being debated.
This presentation details research initiated to better understand the influence of moisture on delamination using capacitance measurements. Measurable changes in capacitance were recorded in the PCBs after each reflow. Discrimination between different test structures and MSL exposures strongly suggests the capacitance approach measures true material degradation rather than an increase in resistance at contact pads due to oxidation. However,contact resistance should be quantified in a next round of testing. Strong differences in shield-over-shield capacitance between test structures are interesting and should also be further characterized.