The utilization of embedded components has increased across many applications in various industries,and with rapid emergence of technologies and the need to secure IP,new methodologies are being used to satisfy market requirements. As design teams face constant pressure to implement the latest embedded component technologies,such as embedded SoCs directly within the laminate,many workarounds are used during the design process,leading to costly errors during the manufacturing process. In this session,we will explore the various technologies and challenges with embedded components for current and future designs. We will also discuss new methods to accurately model and design using the latest embedded component technologies,how to eliminate work-arounds during the design process,and how to minimize errors in manufacturing.

The demands on volume delivery and positioning accuracy for solder paste deposits are increasing as the size and complexity of circuits continue to develop in the electronics industry. According to the iNEMI 2013 placement accuracy for these kinds of components will reach 6 sigma placement accuracy in X and Y of 30 um by 2023 [3]. This study attempts to understand the dependencies on piezo actuation pulse profile on jetting deposit quality,especially focused on positioning,satellites and shape. The correlation of deposit diameter and positioning deviation as a function of piezo actuation profile shows that positioning error for deposits increase almost monotonically with decreasing droplet volume irrespective of the piezo-actuation profile. The trends for shape and satellite levels are not as clear and demand further study.

Solder paste printing is known to be one of the most difficult processes to quality assure in electronic manufacturing. The challenge increases as the technology development moves toward a mix between large modules and small chip components on large and densely populated printed circuit boards. Having a process for quality assurance of the solder paste print is fast becoming a necessity. This article describes a method to ensure quality secured data from both solder paste printers and inspection machines in electronic assembly manufacturing. This information should be used as feedback in order to improve the solder paste printing process.

Transmission of data is a major driver in the electronics industry. Higher data volumes,high speed data transfer and short time signal transmission have to be realized to meet these requirements. To minimize losses,the Radio Frequency (RF) application and standard PCB requirements have to be realized on the same board. This additional technology puts additional demands on the PCB. To achieve these targets,the material,build up and design need to be adjusted to both requirements. Test procedures,focused on particular RF properties have to be considered as well.
This paper examines the development of mixed Microwave and Digital Multilayer printed circuit boards (PCB) for high density application. The major innovations include Radio Frequency (RF) functions,coupled with stacked copper filled Microvia and High Density Interconnection (HDI) technologies,made together into one multilayer construction.
The aim of this study shows the development and validation of raw materials to meet dielectric,power and signal loss properties. From a manufacturing point of view,asymmetrical build up of raw materials with specific RF properties and other PCB raw materials will be investigated,to demonstrate the compatibility of mixed materials in a multilayer PCB´s.
This research was carried out by the company in cooperation with MIDIMU,a European Consortium Project.

Cavity technology in a Printed Circuit Board (PCB) has existed for many years. The methodology to create the cavity in the PCB has evolved over time as technologies have advanced and the manufacturing process varies by the individual PCB fabricator as well as the reasons for using the cavity technology. For the purpose of this paper,a cavity will be defined as a hole in the PCB going from the outer copper layer to an inner copper layer,but not completely through the PCB. The cavity design and assembly issues identified during the design of experiments (DOEs),the findings,reliability results,and conclusions will be discussed in this paper.

Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the active and passive components. There are many ways to increase the packaging density and a few examples would be to stack them with Package on Package (PoP),fine pitch CSP’s,01005 and last but not least reduced component to component spacing for active and passive components.
The use of fine pitch CSP,PoP component’s and 01005(Imperial) poses a number of challenges for PCB Design,SMT Assembly process and reliability and by placing them closer together many of these challenges will be magnified. A feasible assembly process must be achieved. The assembly process ranges all the way from screen-printing,placement and reflow soldering in air or nitrogen.Many factors influence the quality of the assembly process and with the reduced pitch and component spacing,the process capabilities for both assembly and PCB fabrication will be tested to its limit and beyond.
In many cases these assemblies also require a rework process either in the manufacturing facility or at repair centers when the product fails in the field during usage. In addition the correct materials such as PCB material,PCB surface finish,solder paste,dipping flux and PCB design need to be selected to ensure high yielding,cost effective and reliable interconnects. Of course,the mechanics of the products makes a big difference as well but it is very product dependent. Many of today’s products leave little room for designing the mechanics in the most reliable way due to total cost and overall look and size of the products.
This paper will discuss different layouts,assembly and material selections to reduce component to component spacing down to 100-125um (4-5mil) from today’s mainstream of 150-200um (6-8mil) component to component spacing.

The printed circuit board assembly industry has long embraced the “Smaller,Lighter,Faster” mantra for electronic devices,especially in our ubiquitous mobile devices. As manufacturers increase smart phone functionality and capability,designers must adopt smaller components to facilitate high-density packaging. Measuring over 40% smaller than today’s 0402M
(0.4mmx0.2mm) microchip,the new 03015M (0.3mm×0.15mm) microchip epitomizes the bleeding-edge of surface mount component miniaturization. This presentation will explore board and component trends,and then delve into three critical areas for successful 03015M
adoption: placement equipment,assembly materials,and process controls. Beyond machine requirements,the importance of taping specifications,component shape,solder fillet,spacing gap,and stencil design are explored. We will also examine how Adaptive Process Control can increase production yields and reduce defects by placing components to solder position rather than pad. Understanding the process considerations for 03015M component mounting today will help designers and manufacturers transition to successful placement tomorrow.

Higher-speed signal transmission is increasingly required on a printed circuit board to handle massive data in electronic systems. So,signal transmission loss of copper wiring on a printed circuit board has been studied. First,total signal loss was divided into dielectric loss and conductor loss quantitatively based on electromagnetic theory. In particular,the scattering loss due to surface roughness of copper foil has been examined in detail and the usefulness of the copper foil with low surface roughness has been demonstrated.

An IPC specification is a consensus document that specifies attributes relevant to the plated surface. Plating specifications are designed to be applicable to a wide range of products types. As product continues to evolve and new product types are needed,it is necessary for the committee to periodically revise its documents. Between revisions it may be necessary for designers to take exception with one or more of the provision in the specification.

The IPC 4-14 Plating subcommittee has issued a series of specifications starting with ENIG Specification 4552 in 2002 to ENEPIG Specification 4556 in 2013. In between it has issued specification for Immersion Silver 4553 and for Immersion Tin 4554. The committee has made a sincere effort to issue an OSP specification 4555. This effort did not produce results for various reasons.

The committee has completed a revision of the immersion silver specification 4553-A and is presently working on revising the ENIG specification 4552-A.

As new surface finishes come to the forefront the committee will attempt to add new specifications. Examples are palladium on copper,ENIS electroless nickel immersion silver,and plasma nano coatings.

Although traditional plating like electrolytic acid copper and electrolytic tin have been in use since the 1980s,it may be necessary to specify plated attributes as the demands for controlled impedance for high frequency,harsh use environments like automotive,as well as very high reliability like aerospace and medical,put new demands on these plated surfaces.

This paper will give an update of the completed and present activities of the plating committee. It will also attempt to layout a roadmap for future specifications.

In order to provide the functionality in today’s electronics,printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces,this means no nodules,no pits,and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However,the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble,phosphorized,copper anodes introduce particulate and limits the ability to control plating distribution.
The companies worked together to evaluate a new approach using insoluble anodes that are isolated from the main plating bath. Insoluble anodes are known to eliminate the particulate,provide consistent anode area and shape the anode to match the plated part. But isolating the insoluble anode dramatically reduces high consumption of organic additives typical with insoluble anodes. This new approach limits additive breakdown and & consumption normally seen at the soluble anode surface. The end result is a surface free of nodules,pits,and precise control of copper thickness distribution minimizing the impact of breakdown products.
This paper is to document the results from prototype testing through implementation into production. The system was first tested in pilot tanks at the companies to determine the impact on nodules and surface distribution. Data was generated looking at impact of anode design on plating distribution and surface for any defects. This data was utilized to design a full scale production line that is being used to quantify process improvement over existing production equipment. The goal for the work being done is a perfect copper surface.