Pad cratering failure has emerged due to the transition from traditional SnPb to SnAgCu alloys in soldering of printed circuit assemblies. Pb-free-compatible laminate materials in the printed circuit board tend to fracture under ball grid array pads when subjected to high strain mechanical loads. In this study,two Pb-free-compatible laminates were tested,plus one dicy-cure non-Pb-free-compatible as control. One set of these samples were as-received and another was subjected to five reflows. It is assumed that mechanical properties of different materials have an influence on the susceptibility of laminates to fracture. However,the pad cratering phenomenon occurs at the layer of resin between the exterior copper and the first glass in the weave. Bulk mechanical properties have not been a good indicator of pad crater susceptibility. In this study,mechanical characterization of hardness and Young’s modulus was carried out in the critical area where pad cratering occurs using nano-indentation at the surface and in a cross-section. The measurements show higher modulus and hardness in the Pb-free-compatible laminates than in the dicy-cured laminate. Few changes are seen after reflow – which is known to have an effect -- indicating that these properties do not provide a complete prediction. Measurements of the copper pad showed significant material property changes after reflow.

Many opportunities exist for flexible circuits in high temperature applications (Automotive,Military,Aerospace,Oil and Gas). Flex circuits in these applications have been hindered by a lack of materials that can survive higher temperatures. Some materials,especially some thermoset adhesives,break down over time at higher temperature,becoming brittle or losing adhesion to copper. Polyimides tend to perform much better under high temperature. The other issue is the lack of good test methods to verify that flex materials can survive higher temperatures. Several methods for testing copper clad laminates exist but there are very few for coverlays and bondplies. We will discuss different test methods for measuring high temperature capability including the new IPC Service Temperature test. We will also report on test results for various flexible materials and our recommendations for the best flexible materials for high temperature applications. This will include development work on new flex materials for high temperature applications.

The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology,the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated,the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that itis sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes,blind,or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly. The test vehicles will be production-built hardware from multiple suppliers over a 4-year time period,of 2010 to 2014,of polyimide and epoxy constructions. Both 152-µmand 203-µmdiameter microvias will be reviewed. It will be shown that theinitialIPC-TM-650 Number 2.6.26 DC Current Induced Thermal Cycling Test,dated May 2001 default conditions were not sufficient to adequately screen for microvia manufacturing inconsistencies and that,with a few changes to the current testing,high-reliability product could be screened quickly for current technology.

This paper describes the purpose,methodology,and results to date of thermal endurance testing performed at the company. The intent of this thermal aging testing is to establish long term reliability data for printed wiring board (PWB) materials for use in applications that require 20+ years (100,000+ hours) of operational life under different thermal conditions. Underwriters Laboratory (UL) testing only addresses unclad laminate (resin and glass) and not a fabricated PWB that undergoes many processing steps,includes copper and plated through holes,and has a complex mechanical structure. UL testing is based on a 5000 hour expected operation life of the electronic product. Therefore,there is a need to determine the dielectric breakdown / degradation of the composite printed circuit board material and mechanical structure over time and temperature for mission critical applications. Thermal aging testing consisted of three phases. Phase I –A 500 hour pre-screen at four fixed temperatures following IEEE98 A.1 and UL746B 20A1(completed). Phase II –Short term aging for 1000 hours at four revised,fixed temperatures. Plated through hole reliability testing using IST and HATS was also completed. Phase III –Long term aging for 25,000 hours at five,revised fixed temperatures. This paper will discuss results of this testing to date

Advances in miniaturized electronic devices have led to the evolution of microvias in high density interconnect (HDI) circuit boards from single-level to stacked structures that intersect multiple HDI layers. Stacked microvias are usually filled with electroplated copper. Challenges for fabricating reliable microvias include creating strong interface between the base of the microvia and the target pad,and generating no voids in the electrodeposited copper structures. Interface delamination is the most common microvia failure due to inferior quality of electroless copper,while microvia fatigue life can be reduced by over 90% as a result of large voids,according to the authors’ finite element analysis and fatigue life prediction. This paper addresses the influence of voids on reliability of microvias,as well as the interface delamination issue. In a prior study,the authors investigated stress levels of copper-filled microvias with spherical voids of different sizes. Besides void size,void shape and microvia aspect ratio also affect the stress levels,and hence reliability of voided microvias. In this paper,stacked microvias with different void shapes and aspect ratios were modeled using finite element method. Stress distributions of these microvia models under cyclic thermal loading were examined to determine the effects of the voids on the reliability of microvias at different circumstances. The finite element modeling results demonstrated that conical voids resulted in higher stress levels in microvias than spherical voids of the same size. For the same void shape,larger voids increased the stress level,except for very small spherical voids which reduced the maximum stress in the microvias. To study the delamination issue,the very thin layer of electroless copper was simulated between the base of the microvia and the target pad. It is assumed that the delamination was due to fracture within the electroless copper layer. The fracture toughness parameter in terms of stress intensity factor was calculated under different initial crack length and thermal loading conditions to characterize the likelihood of the delamination.

As consumers become more reliant on their handheld electronic devices and take them into new environments,devices are increasingly exposed to situations that can cause failure. In response,the electronics industry is making these devices more resistant to environmental exposures. Printed circuit board assemblies,handheld devices and wearables can benefit from a protective conformal coating to minimize device failures by providing a barrier to environmental exposure and contamination. Traditional conformal coatings can be applied very thick and often require thermal or UV curing steps that add extra cost and processing time compared to alternative technologies. These coatings,due to their thickness,commonly require time and effort to mask connectors in order to permit electrical conductivity. Ultra-thin fluorochemical coatings,however,can provide excellent protection,are thin enough to not necessarily require component masking and do not necessarily require curing. In this work,ultra-thin fluoropolymer coatings were tested by internal and industry approved test methods,such as IEC (ingress protection),IPC (conformal coating qualification),and ASTM (flowers-of-sulfur exposure),to determine whether this level of protection and process ease was possible. The fluoropolymer coatings chosen for this test were created in a range of coating solids and application thicknesses (100 nm to 30 µm). Being a solution,these coatings were easy to apply by either vertical dip or atomized spray methods. In this study,it was found that both the application method and the thickness of the fluoropolymer coating played a significant role in the level of corrosion resistance and water/vapor repellency results. The data generated demonstrates a general correlation of how thick an ultra-thin fluoropolymer coating must be in order to achieve certain levels of protection.

Conformal Coatings are often used to increase the reliability of electronic assemblies operating in harsh or corrosive environments where the product would otherwise fail prematurely. Conformal coatings are often qualified to international standards,intended to enable users to better differentiate between suitable conformal coating chemistries,but always on a flat test coupon,which is not representative of real world use conditions. In order to better correlate international standards with real world-use conditions,three-dimensional Surface Insulation Resistance (SIR) test boards have been manufactured with dummy components representative of those commonly used on printed circuit assemblies. A variety of commercially available,internationally qualified,conformal coatings have been applied to these coupons by a variety of common methodologies including dip,spray and selective-spray,at a variety of thicknesses. The applied conformal coatings were cured in accordance with the manufacturer’s recommendations. The conformal coating thickness and coverage over critical areas was assessed by non-invasive optical methods. The coated samples were then subjected to 1000 thermal shock cycles (-65°C to + 125°C) and salt-mist cycles to represent typical end use qualification testing. Voltage was applied to the SIR boards during the salt-spray test regime to better correlate to real use conditions. The corrosion evident on assemblies was visually assessed by optical microscopy under 4-40X magnification and compared with the measured SIR to assess corrosion resistance of the various process combinations. Lead-free solder was used exclusively for this test,and water-washable,cleanable ‘no-clean’ and no-clean flux samples were included,to investigate the effect of cleaning on the overall reliability of the coated system. Conformal coating thickness and coverage were assessed for the various coating techniques. The results of the thermal shock and powered salt-spray test results are correlated back to the application method,coating thickness,flux,cleaning and coating chemistry to determine the best overall process and material combinations for high reliability applications.

In this investigation a test matrix was completed utilizing 900 electrodes (small circuit board with parallel copper traces on FR-4 with LPI soldermask at 6,10 and 50 mil spacing): 12 ionic contaminants were applied in five concentrations to three different spaced electrodes with five replicas each(three different bare copper trace spacing / five replications of each with five levels of ionic concentration). The investigation was to assess the electrical response under controlled heat and humidity conditions of the known applied contamination to electrodes,using the IPC SIR (surface insulation resistance) J-STD 001 limits and determine at what level of contamination and spacing the ionic / organic residue has a failing effect on SIR.

The iNEMI technical subcommittee on creep corrosion is developing a flowers-of-sulfur (FOS) based qualification test for creep corrosion on printed-circuit boards (PCBs). In phase 1 of the project,the performances of FOS chambers of two designs were evaluated by measuring the corrosion rates of copper and silver foils. This paper deals with the phase 2A of the project in which PCBs with immersion silver (ImAg) and lead-free hot-air-surface-level (HASL) finishes soldered with rosin and organic acid fluxes were tested. The test variables were chamber temperature,type of saturated salt solution determining the relative humidity,chamber setup and particulate contamination. The results of test runs conducted at 4 laboratories involved in the round robin testing are very promising. The ImAg PCBs soldered with organic acid flux suffered the most creep corrosion in agreement with the generally agreed to field experience. There were fewer instances of creep corrosion on test PCBs with ImAg finish soldered with rosin flux and on test PCBs with lead-free HASL finish. Creep corrosion was generally associated with plated through holes (PTHs). Contaminating the test PCBs with ammonium salts contributed to more creep corrosion but made the test somewhat less discriminatory in that even test PCBs with HASL finish soldered with rosin flux suffered some creep corrosion.

Head-In-Pillow (HIP) defects,in which the BGA solder balls and paste deposit come in contact but do not coalesce,have proven to be a major problem since transitioning to RoHS soldering. Component warp can contribute significantly to HIP defects. While process engineers can make changes,such as reflow profile adjustment,to reduce the number of defects,component warp is generally dictated by component design. However,it is possible to counter the component warp by adjusting the stencil design. This paper outlines a method of refining the stencil design process to achieve the best results.